Digital Logic and Microprocessors

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented. temp$\leftarrow$reg & mask Branch to label if temp is non-zero. The variable temp is a temporary register. For correct emulation, the variable mask must be generated by

Consider the following assembly language program for a hypothetical processor A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; B ^{_$\leftarrow$} 0 MOV C, #8 ; C ^{_$\leftarrow$} 8 Z: CMP C, #0 ; Compare C with 0 JZX ; Jump to X if zero flag is set SUB C, #1 ; C ^{_$\leftarrow$} C - 1 RRC A, #1 ; right rotate A through carry by one bit. Thus: ; if the initial values of A and the carry flag are a₇… a₀ and ; instruction will be c₀a₇…a₁ and a₀ respectively JCY ; jump to Y if carry flag is set JMP Z ; jump to Z Y: ADD B, #1 ; B ^{_$\leftarrow$} B + 1 X: If the initial value of register A is A0, the value of register B after the program execution will be

Consider the following assembly language program for a hypothetical processor A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; B $\leftarrow$0 MOV C, #8 ; C$\leftarrow$8 Z: CMP C, #0 ; Compare C with 0 JZX ; Jump to X if zero flag is set SUB C, #1 ; C $\leftarrow$ C -1 RRC A, #1 ; right rotate A through carry by one bit. Thus: ; if the initial values of A and the carry flag are a₇… a₀ and ; instruction will be c₀a₇…a₁ and a₀ respectively JCY ; jump to Y if carry flag is set JMP Z ; jump to Z Y: ADD B, #1 ; B $\leftarrow$ B + 1 X:

Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions? ADD R2, R1, R0 R2 $\rightarrow$ R1 + R0 MUL R4, R3, R2 R4$\rightarrow$ R3 * R2 SUB R6, R5, R4 R6 $\rightarrow$R5 - R4

Given the following state table of an FSM with two states A and B, one input and one output:

If the initial state is A = 0, B = 0, what is the minimum length of an input string which will take the machine to the state A = 0, B = 1 with Output = 1?

In a simplified computer the instructions are: OP R_j , R_i - Performs R_j OP R_i and stores the result in register . R_i OP m, R_i - Performs val i OP R_i and stores the result in R_i. val denotes the content of memory location m. MOV m, R_i - Moves the content of memory location m to register R_i MOV R_i , m - Moves the content of register R_i to memory location m. The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block: t₁ = a + b t₂ = c + d t₃ = e - t₂ t₄ = t₁ - b Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

Consider the following circuit composed of XOR gates and non-inverting buffers

The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time

1. If the following waveform is applied at input A, how many transition(s) (change of logic levels) Occur (s) at B during the interval from 0 to 10 ns?

We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $ c_{out}$. Which one of the following options correctly identifies the overflow condition?

Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ and $ i_{2}=\left \langle w_{2}, x_{2}, y_{2},z_{2}\right \rangle $ , we would like the function to remain true as the input changes from $ i_{1}$ to $ i_{2}$ ($ i_{1}$ and $ i_{2}$ differ in exactly one bit position) without becoming false momentarily. Let $ f(w,x,y,z)=\sum (5,7,11,12,13,15)$ . Which of the following cube covers of $f$ will ensure that the required property is satisfied?