Digital Logic and Microprocessors

Given the following state table of an FSM with two states A and B, one input and one output:

If the initial state is A = 0, B = 0, what is the minimum length of an input string which will take the machine to the state A = 0, B = 1 with Output = 1?

In a simplified computer the instructions are: OP R_j , R_i - Performs R_j OP R_i and stores the result in register . R_i OP m, R_i - Performs val i OP R_i and stores the result in R_i. val denotes the content of memory location m. MOV m, R_i - Moves the content of memory location m to register R_i MOV R_i , m - Moves the content of register R_i to memory location m. The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block: t₁ = a + b t₂ = c + d t₃ = e - t₂ t₄ = t₁ - b Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

Consider the following circuit composed of XOR gates and non-inverting buffers

The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time

1. If the following waveform is applied at input A, how many transition(s) (change of logic levels) Occur (s) at B during the interval from 0 to 10 ns?

We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $ c_{out}$. Which one of the following options correctly identifies the overflow condition?

Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ and $ i_{2}=\left \langle w_{2}, x_{2}, y_{2},z_{2}\right \rangle $ , we would like the function to remain true as the input changes from $ i_{1}$ to $ i_{2}$ ($ i_{1}$ and $ i_{2}$ differ in exactly one bit position) without becoming false momentarily. Let $ f(w,x,y,z)=\sum (5,7,11,12,13,15)$ . Which of the following cube covers of $f$ will ensure that the required property is satisfied?

The control signal functions of a 4-bit binary counter are given below (where X is “don't care”): Clear Clock Load Count Function

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function P_i for inputs A_i and B_i are given by:
P_i = A_i $\oplus$ B_i and G_i = A_i B_i The expressions for the sum bit S_i and the carry bit C_i+1 of the look-ahead carry adder are given by: S_i = P_i C_i and C_i+1 = G_i + P_i C_i, where C_o is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_i and G_i are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with 3 2 1 0 4 S ,S ,S ,S and C as its outputs are respectively:

A 1-input, 2-output synchronous sequential circuit behaves as follows: Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk+nk=k). The circuit outputs 00 until one of the following conditions holds. zk - nk=2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?