Computer Knowledge

Digital Logic and Microprocessors

735 Questions

Digital logic and microprocessors form the core of computer science, covering logic gates, combinational and sequential circuits, and CPU architecture. These topics are crucial for computer knowledge sections in technical exams. Test your digital electronics basics here.

Logic gates and circuitsCombinational vs sequential circuitsMicroprocessor instructionsTruth tables and boolean functions

Digital Logic and Microprocessors Questions

Multiple choice

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncompensated forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

  1. 4 time units

  2. 6 time units

  3. 10 time units

  4. 12 time units
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Multiple choice

Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

  1. Q2'

  2. Q2+ Q1
  3. (Q1 $\oplus$ Q2)'
  4. Q1 $\oplus$ Q2
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Counter counts the no. of signal inversion change of states. Sequence input is 0 − 2 − 3 − 1 − 0 Binary 00 − 10 − 11 − 01 − 00 to generate signals if we XOR gate then it outputs 1 if both are different. So output sequence would be. 0 − 1 − 0 − 1 − 0 & the sequence would be counted. So. X = Q1$\oplus$Q2

Multiple choice

Consider two processes P1 and P2 accessing the shared variables X and Y protected by two binary semaphores Sx and Sy respectively, both initialized to 1. P and V denote the usual semaphore operators, where P decrements the semaphore value and V increments the semaphore value. The pseudo-codes of P1 and P2 are as follows:

In order to avoid deadlock, the correct operators at L1,L2,L3 and L4 are respectively

  1. P(SY),P(SX);P(SX),P(SY)

  2. P(SX),P(SY);P(SY),P(SX)

  3. P(SX),P(SX);P(SY),P(SY)

  4. P(SX),P(SY);P(SX),P(SY)
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Here semaphores are required to obtain mutual exclusion since both access X & Y. So at L1 P (Sx) which means now S wait x = at L2 P (Sy) Sy wait, this prevents process P2 to start access X &Y. V(Sx) & V(Sy) in the end of P1 makes Sx & Sy signal so that at L3 & L4 P(Sx) & P(Sy) can start.

Multiple choice

Two nibble adder can be implemented by (without initial carry)

  1. 4 full adderscomplementary

  2. 3 full adder and a half adder

  3. 4 half adder

  4. 2 half and 2 full adders
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

A nibble is 4 bits. When adding two 4-bit numbers without an initial carry, the least significant bit (LSB) position only needs a half adder since there's no carry-in. The remaining 3 bit positions each require a full adder to handle the carry-out from the previous stage. Therefore, 3 full adders and 1 half adder are needed.

Multiple choice

How many gates (minimum) are needed for a 3-bit up counter using standard binary and using T flip-flop?

Assume unlimited fan-in.

  1. 4

  2. 3

  3. 2

  4. 1
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

A 3-bit up counter using T flip-flops requires minimum gates when exploiting the toggle pattern. With unlimited fan-in, only 2 gates are needed: the first T flip-flop toggles every clock (no gate needed), while the second and third require enable logic that can be implemented with just 2 gates total using AND/OR combinations.

Multiple choice

A sequential circuit has one input and one output. In the input sequence whenever a pattern 010 or 0001 is detected, the output becomes 1 when the last symbol of the pattern is received. Otherwise, the output equals to 0. What will be the minimum number of states of the equivalent state diagram of this synchronous sequential circuit?

  1. 4

  2. 5

  3. 6

  4. 7
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

To detect patterns 010 and 0001, we need states representing partial matches. State diagram needs: initial state (S0), after '0' (S1), after '01' (S2), after '010' (S3 - output 1), after '00' (S4), after '000' (S5), after '0001' (S6 - output 1). However, some states can be merged, and the minimal implementation requires 5 states to track all necessary prefix information without redundancy.