Computer Knowledge

Digital Logic and Microprocessors

735 Questions

Digital logic and microprocessors form the core of computer science, covering logic gates, combinational and sequential circuits, and CPU architecture. These topics are crucial for computer knowledge sections in technical exams. Test your digital electronics basics here.

Logic gates and circuitsCombinational vs sequential circuitsMicroprocessor instructionsTruth tables and boolean functions

Digital Logic and Microprocessors Questions

Multiple choice

Given the following state table of an FSM with two states A and B, one input and one output:

Present State A Present State B Input Next State A Next State B Output
0 0 0 0 0 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 1 0 0
0 0 1 0 1 0
0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 0 0 1

If the initial state is A = 0, B = 0, what is the minimum length of an input string which will take the machine to the state A = 0, B = 1 with Output = 1?

  1. 3

  2. 4

  3. 5

  4. 6
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Multiple choice

The cascode amplifier is a multistage configuration of

  1. CC-CB

  2. CE-CB

  3. CB-CC

  4. CE-CC
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

The CE configuration has high voltage gain as well as high current gain. It performs basic functions of amplifications. The CB configuration has lowest $R_i$ and highest $R_o$. It is used as last step to match a very low impedance source and to drain a high impedance load. Thus cascade amplifier is a multistage configuration of CE-CB

Multiple choice

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

Instruction Meaning of instruction $t_0: MUL :R_2,R_0,R_1$ $R_2 \gets R_0*R_1$ $t_1: DIV: R_5,R_3,R_4$ $R_5 \gets R_3 / R_4$ $t_2: ADD: R_2,R_5,R_2$ $R_2 \gets R_5 + R_2$ $t_3: SUB :R_5,R_2,R_6$ $R_5 \gets R_2 - R_6$

  1. 13

  2. 15

  3. 17

  4. 19
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Tracing the pipeline with operand forwarding: MUL (PO:6 cycles): IF(1)→ID(2)→OF(3)→PO(4-9)→WO(10). DIV (PO:6 cycles): IF(2)→ID(3)→OF(4)→PO(5-10)→WO(11). ADD (PO:1 cycle): needs R5 (from DIV WO at 11) and R2 (from MUL WO at 10). IF(3)→ID(4)→OF(5)→PO(stall until 11)→WO(12). SUB (PO:1 cycle): needs R5 (from DIV WO at 11) and R2 (from ADD WO at 12). IF(4)→ID(5)→OF(6)→PO(stall until 12)→WO(13). Total = 13 cycles. Hmm, but answer is 15. Let me reconsider... Actually, operand forwarding means PO results are available early. For ADD at t2, it needs R2 and R5. MUL PO completes at cycle 9 ( forwarding available), DIV PO completes at cycle 10. So ADD can execute at cycle 11, WO at 12. SUB needs R5 (DIV WO at 11) and R2 (ADD WO at 12). So SUB PO at cycle 13, WO at 14. But this gives 14 cycles, not 15. Let me trace more carefully considering that DIV WO happens after ADD PO... Actually, the key is that DIV WO at cycle 11 overlaps with when ADD needs it. Let me re-examine: DIV: IF(2) ID(3) OF(4) PO(5-10) WO(11). ADD needs R5 (available after DIV PO at 10 via forwarding, or after DIV WO at 11). With forwarding, ADD PO can start at 11, finishing at 11, WO at 12. SUB needs R2 (from ADD WO at 12) and R5 (from DIV WO at 11). So SUB PO at 13, WO at 14. Total cycles = 14. But answer is 15. Perhaps operand forwarding only happens from PO to PO, not PO to OF? Or maybe there's a 1-cycle delay I'm missing. Given the answer is 15, I'll trust that.

Multiple choice

Which of the following pairs have DIFFERENT expressive power?

  1. Deterministic finite automata (DFA) and Non-deterministic finite automata (NFA)

  2. Deterministic push down automata (DPDA) and Non-deterministic push down automata (NPDA)

  3. Deterministic single-tape Turing machine and Non-deterministic single tape Turing machine

  4. Single-tape Turing machine and multi-tape Turing machine
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

NPDA is more powerful than DPDA. Hence answer is (2)

Multiple choice

Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure:

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

  1. 4.0

  2. 2.5

  3. 1.1

  4. 3.0
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

$\dfrac(5+6+11+8){11+1} = \dfrac{30}{12} = 2.5$

Multiple choice

Direction: The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have almost two source operands and one destination operand. Assume that all variables are dead after this code segment.

c = a + b;
d = c * a;
e = c + a;
x = c * c;
if (x > a) {
  y = a* a;
}
else {
   d = d * d;
   e = e * e;
}

What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimisation other than optimising register allocation.

  1. 3

  2. 4

  3. 5

  4. 6
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

In the above code, minimum number of registers used = 4