Multiple choice

For a pipelined CPU with a single ALU, consider the following situations I. The j + 1-st instruction uses the result of the j-th instruction as an operand II. The execution of a conditional jump instruction III. The j-th and j + 1-st instructions require the ALU at the same time

Which of the above can cause a hazard?

  1. I and II only

  2. II and III only

  3. III only

  4. All the three
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Case 1 is here of data dependency, this can't be safe with single ALU so read after write. Case 2 Conditional jumps are always hazardous they create conditional dependency in pipeline Case 3 this is write after read problem or concurrency dependency so hazardous All the three are hazardous.

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