Digital Logic and Microprocessors

Question 1

Multiple choice

Given two three bit numbers a₂ a₁ a₀ and b₂ b₁ b₀ and c, the carry in, the function that represents the carry generate function when these two numbers are added is:

a₂ b₂ + a₂ a₁ b₁ + a₂ a₁ a₀ b₀ + a₂ a₀ b₁ b₀ + a₁ b₂ b₁ + a₁ a₀ b₂ b₀ + a₀ b₂ b₁ b₀
a₂ b₂ + a₂ a₁ b₀ + a₂ a₁ b₁ b₀ + a₁ a₀ b₂ b₁ + a₁ a₀ b₂ + a₁ a₀ b₂ b₀ + a₂ a₀ b₁ b₀

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Answer

a₂+ b₂ + (a_2$\oplus$b₂) (a₁ + b₁ +(a_1$\oplus$b₁) (a₀+ b₀))

Question 2

Multiple choice

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

7
8
9
10

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Answer

0, 1, 2, 3, 4, 5

Answer

2ⁿ⁻¹ line to 1 line

Answer

f = x1x2 + x1'x2'

Answer

1, 2, 5, 3, 7, 6, 4

Answer

$\sum$ (1,4,5)

Answer

AC = 1 and CY = 0

Answer

Outputs the sum of the present and the previous bits of the input.

Question 3

Multiple choice

The control signal functions of a 4-bit binary counter are given below (where X is “don't care”): Clear Clock Load Count Function

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

0, 3, 4
0, 3, 4, 5
0, 1, 2, 3, 4

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Question 4

Multiple choice

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

2ⁿ line to 1 line
2ⁿ⁺¹ line to 1 line
2ⁿ⁻² line to 1 line

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Question 5

Multiple choice

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function P_i for inputs A_i and B_i are given by:
P_i = A_i $\oplus$ B_i and G_i = A_i B_i The expressions for the sum bit S_i and the carry bit C_i+1 of the look-ahead carry adder are given by: S_i = P_i C_i and C_i+1 = G_i + P_iC_i, where C_o is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_i and G_i are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with 3 2 1 0 4 S ,S ,S ,S and C as its outputs are respectively:

6, 3
10, 4
6, 4
10, 5

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Question 6

Multiple choice

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates?

2
3
4
5

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Question 7

Multiple choice

A 1-input, 2-output synchronous sequential circuit behaves as follows: Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk+nk=k). The circuit outputs 00 until one of the following conditions holds. zk - nk=2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?

5
6
7
8

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C Correct answer

Explanation

The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output for particular inputs decide states.

i/p	op 1	op 2	State
0	0	0	Initial
0	0	1	$n_k - z_k = 2$
0	1	0	$z_k - n_k = 2$
1	0	0	Not applicable
1	0	0	Initial
1	0	1	$n_k - z_k = 2$
1	1	0	$z_k - n_k = 2$
0	0	1	$n_k - z_k = 2$
1	1	1	is correct

using 3 bits we require $ 2^3 - 1 = 7 $ states here

Question 8

Multiple choice

Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc).

Which of the following is true?

f = x1' + x2
f = x1'x2 + x1x2'
f = x1 + x2

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Question 9

Multiple choice

Consider the circuit given below the initial state Q₀ = 1,Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂+ 2Q₁+ Q₀

Which one of the following is the correct state sequence of the circuit?

1, 3, 4, 6, 7, 5, 2
1, 2, 7, 3, 5, 6, 4
1, 6, 5, 7, 2, 3, 5

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Question 10

Multiple choice

Consider the following logic circuit whose inputs are functions f₁, f₂, f₃ and output is f

Given that f1(x,y, z) = $\sum$(0,1,3,5) f2(x,y,z) = $\sum$(6,7), and f (x,y,z) = $\sum$(1,4,5) f3 is

$\sum$ (6,7)
$\sum$ (0,1,3,5)
None of the above

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Question 11

Multiple choice

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the following 8085 program? MIV H, 5DH MIV L, 6BH MIV L, 6BH ADD L

AC = 0 and CY = 0
AC = 1 and CY = 1
AC = 0 and CY = 1

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Question 12

Multiple choice

Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00,01,10,11 respectively and f is the output of the multiplexor. EN is the Enable input.

The function f (x,y,z) implemented by the above circuit is

xyz'
xy + z
x + y
None of the above

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Question 13

Multiple choice

The finite state machine described by the following state diagram with A as starting state, where an arc label is $\dfrac{x}{y}$ and x stands for 1-bit input and y stands for 2-bit output.

Outputs 01 whenever the input sequence contains 11
Outputs 00 whenever the input sequence contains 10
None of the above.

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Question 14

Multiple choice

Consider the following circuit with initial state Q₀ = Q₁ = 0. The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C ; the clock of C 40 nanosecond. Which one is the correct plot of Y

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Question 15

Multiple choice

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,...9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit $\ge$ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

2
3
4
5

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Digital Logic and Microprocessors

Digital Logic and Microprocessors Questions