Computer Knowledge

Digital Logic and Microprocessors

735 Questions

Digital logic and microprocessors form the core of computer science, covering logic gates, combinational and sequential circuits, and CPU architecture. These topics are crucial for computer knowledge sections in technical exams. Test your digital electronics basics here.

Logic gates and circuitsCombinational vs sequential circuitsMicroprocessor instructionsTruth tables and boolean functions

Digital Logic and Microprocessors Questions

Multiple choice technology embedded technologies

Albin,Ethernetswitch and busco functionality are combined in to one FPGA in spb4 and is called as

  1. PIX

  2. package interfacing switch

  3. E-SPIM

  4. All the above options
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

On the SPB4 board, the Albin, Ethernet switch, and busco functionalities are integrated into a single FPGA known as PIX (Packet Interconnect Switch). Other options represent incorrect acronyms or alternate components.

Multiple choice technology

Variable ports can be

  1. a. assigned to Input ports

  2. b. assigned to Output port

  3. c. connected to successive transformation

  4. d. Filter transformation
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Variable ports within a transformation can be used to calculate intermediate values and assigned to output ports of the same transformation. They cannot be assigned to input ports, which receive data from upstream. Variable ports are internal to the transformation and aren't directly connected to downstream transformations.

Multiple choice technology

Variable ports can be

  1. assigned to Input ports

  2. assigned to Output port

  3. connected to successive transformation

  4. None of the Above
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Variable ports in Informatica transformations can only be assigned to output ports within the same transformation. They cannot be assigned to input ports and cannot be directly connected to successive transformations. This is a key constraint of variable port usage and scoping.

Multiple choice technology

In a Digital circuit, what is 1 'AND' 1?

  1. 1

  2. 0

  3. 4

  4. 2
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

In digital logic, the AND operation outputs 1 only when all inputs are 1. Since both inputs are 1, the output is 1. This is the fundamental truth table for the AND gate.

Multiple choice technology

Pulse-triggered flip-flops are called as

  1. master-slave

  2. postponed

  3. edge

  4. level
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Pulse-triggered flip-flops are specifically known as master-slave flip-flops, which use two flip-flops in sequence to synchronize with the clock pulse. Edge-triggered and level-triggered are different triggering mechanisms.

Multiple choice technology

The output of an AND gate is LOW ________.

  1. All the time

  2. when any input is LOW

  3. when any input is HIGH

  4. when all inputs are HIGH
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

AND gate outputs HIGH only when ALL inputs are HIGH. If ANY input is LOW, the output is LOW. This is the defining behavior of an AND gate.

Multiple choice technology

Which is not part of the execution unit (EU)?

  1. Arithmetic logic unit (ALU)

  2. Clock

  3. General registers

  4. Flags
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

The Execution Unit (EU) in microprocessor architecture contains the Arithmetic Logic Unit (ALU) for computations, general-purpose registers for data manipulation, and flag registers to store condition codes and status information. The clock generator is part of the Bus Interface Unit (BIU), not the EU - it provides timing signals for the entire processor.

Multiple choice

Consider the following circuit composed of XOR gates and non-inverting buffers.

enter image description here

The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?

enter image description here

  1. 1

  2. 2

  3. 3

  4. 4
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Due to delays s1= 2 & s2=4 the transistions would occur at time1, 2 & 4.

Time Input (A) Output (B)
0 1 0
I 1 1 0 Transition
II 2 1 0 Transition
III 4 0 1 Transition

So total 3 transistions

Multiple choice

Consider the following circuit composed of XOR gates and non-inverting buffers

GATE 2003

The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time

  1. If the following waveform is applied at input A, how many transition(s) (change of logic levels) Occur (s) at B during the interval from 0 to 10 ns?

GATE 2003 Image 2

  1. 1

  2. 2

  3. 3

  4. 4
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Due to delays s1= 2 & s2=4 the transistions would occur at time1, 2 & 4.

Time Input (A) Output (B)
0 1 0
I 1 1 0 Transition
II 2 1 0 Transition
III 4 0 1 Transition

So total 3 transistions

Multiple choice

For a pipelined CPU with a single ALU, consider the following situations I. The j + 1-st instruction uses the result of the j-th instruction as an operand II. The execution of a conditional jump instruction III. The j-th and j + 1-st instructions require the ALU at the same time

Which of the above can cause a hazard?

  1. I and II only

  2. II and III only

  3. III only

  4. All the three
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Case 1 is here of data dependency, this can't be safe with single ALU so read after write. Case 2 Conditional jumps are always hazardous they create conditional dependency in pipeline Case 3 this is write after read problem or concurrency dependency so hazardous All the three are hazardous.

Multiple choice

Consider the following assembly language program for a hypothetical processor A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; B $\leftarrow$ 0 MOV C, #8 ; C $\leftarrow$ 8 Z: CMP C, #0 ; Compare C with 0 JZX ; Jump to X if zero flag is set SUB C, #1 ; C $\leftarrow$ C - 1 RRC A, #1 ; right rotate A through carry by one bit. Thus: ; if the initial values of A and the carry flag are a7… a0 and ; instruction will be c0a7…a1 and a0 respectively JCY ; jump to Y if carry flag is set JMP Z ; jump to Z Y: ADD B, #1 ; B $\leftarrow$ B + 1 X: If the initial value of register A is A0, the value of register B after the program execution will be

  1. the number of 0 bits in A0

  2. the number of 1 bits in A0

  3. A0

  4. 8
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Here value of B is incremented by 1 only if carry flag is 1, carry is filled using right rotation, so B will store the no. of 1s in A0.