Digital Logic and Microprocessors

A BCD Adder circuit must be able to operate in accordance that if there is carry generated while adding the two 4 bits numbers the result is an invalid sum.

This is the Redundance Law in boolean algebra : (a) A + A B = A (b) A (A + B) = A

Tri-state buffers, also known as 3-state buffers, are combinatorial elements that in addition to providing the two standard logic “0″ and logic “1″ states, can be made to provide a high impedance third state. This third state occurs when the gates output is effectively switched “OFF” or disconnected. This third state is often referred to as an “High-impedance”, “hi-Z“, or just “Z” state.

It is a very direct construction of code that permits correcting single bit errors.

It seems safer, and it is the level of correction and detection most often used in computer memories.

Changing all the bits that are 1 to 0 and all the bits that are 0 to 1 is known as 1's complement.

This specifies how many and which operations to provide and how many complex operations should be included in the design.

It requires one Ex-OR gate for sum generation and one AND gate for carry generation.

It requires one Ex-OR gate for difference generation and one AND gate with a NOT gate for borrow generation.

The output of a NAND gate is low only when all inputs are high at the same time.

A circuitry is required to detect whenever the sum is greater than 01001, so that the correction can be added in.

These instructions provide  means of adding a fixed value into the accumulator in 8085 processor.

Here, the output is high only when both the inputs are low.

This instruction allows the programmer to match the byte in the accumulator with a fixed mask byte, contained in the second byte of the instruction in 8085 processor.

These instructions provide  means of subtracting a fixed value from the contents of the accumulator in 8085 processor.