Computer Knowledge

Digital Logic and Microprocessors

735 Questions

Digital logic and microprocessors form the core of computer science, covering logic gates, combinational and sequential circuits, and CPU architecture. These topics are crucial for computer knowledge sections in technical exams. Test your digital electronics basics here.

Logic gates and circuitsCombinational vs sequential circuitsMicroprocessor instructionsTruth tables and boolean functions

Digital Logic and Microprocessors Questions

Multiple choice
  1. OR gate

  2. Full adder logic chip

  3. Half adder logic chip

  4. NOR-AND gate

  5. NAND gate

Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

The truth table of SUM output of half adder is the same as XOR truth table. So, XOR can be used as a half adder.

Multiple choice
  1. SR terminals are shorted to each other

  2. both inputs of the SR are kept open and a clock is applied

  3. a NOT gate is connected between the SR inputs

  4. S is made 0 and R is made 0

  5. D flip-flop cannot be made by SR flip-flop.

Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

When NOT is connected in between S and R, and S = 1, then R = 0. An applied clock provides output as Q = 1, so D is 1 and Q is also 1. It is the D condition. When S = 0, then R = 1 and the output is Q = 0. This is also the D condition. Other conditions cannot appear. Hence, this configuration will make SR flip-flop a D flip-flop.

Multiple choice
  1. Hardware divider chip, if available; otherwise, by using successive subtraction in an adder chip of its ALU

  2. Hardware divider chip, if available; otherwise, by using successive subtraction in a subtractor chip of its ALU

  3. Shift and subtract algorithm

  4. Shift and add algorithm

  5. Shift and shift algorithm

Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

If the hardware chip is available, the processor will use it for division. If it is not available, then successive subtraction is used and the hardware used by the CPU is adder (using 2's complement representation).

Multiple choice
  1. The propagation delay occurs due to late arrival of the clock in the flip-flop and its own delay.

  2. Total propagation delay is tpd only.

  3. No propagation delay since the clock is available at the same time to all the flip-flops.

  4. Propagation delay is tpd + (n - 1).

  5. Propagation delay does not depend on the clock.

Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Propagation delay is the time required by one flip-flop to respond and produce output, and is given as tpd. In asynchronous counter, the clock is provided only at the first flip-flop. Other flip-flop gets the clock from the Q output of the previous flip-flop. So, time required when the last flip-flop will get the clock is number of flip-flops * response delay of one flip-flop. This total time delay is called propagation delay of the counter. In synchronous counter, all flip-flops get the clock simultaneously.

Multiple choice
  1. Output capacity

  2. Input capacity

  3. Storage capacity

  4. Capacity to drive more than one output

  5. Capacity to have controlled outputs

Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Combinational circuits provide output according to current inputs. It does not save or store its output. So, storage capacity is not a part of combinational circuit.

Multiple choice
  1. Simply parity check

  2. Checksum

  3. Two-dimensional parity check

  4. CRC

  5. None of these

Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Checksums use one's complement arithmetic to detect errors in data transmission. Data is divided into words, summed using one's complement arithmetic, and the complement is sent as the checksum. The receiver performs the same calculation - a non-zero result indicates an error. Parity checks are simpler, CRC is more robust, and 2D parity adds extra dimensions but none use one's complement like checksums.

Multiple choice
  1. 40 msec

  2. 10 msec

  3. 20 msec

  4. 0 msec

  5. 80 msec

Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Ripple counter is asynchronous counter, i.e. output of each flip flop is a clock to next flip flop. In 4 bit ripple counter, no. of flip flop is 4. Maximum delay is 40 msec, the delay propagates from first flip flop to last flip flop in 4 clocks. So, the delay from each flip flop is 40/4 = 10 msec. Delay in first flip flop + delay in second flip flop and so on.