Digital Logic and Microprocessors

Clock signal is concurrently applied to the each flip flop and so the output from each flip flop is simultaneously. Hence, each flip flop will have same i.e. 10 msec.

Ripple counter is asynchronous counter, i.e. output of each flip flop is a clock to next flip flop. In 4 bit ripple counter, no. of flip flop is 4. Maximum delay is 40 msec, the delay propagates from first flip flop to last flip flop in 4 clocks. So, the delay from each flip flop is 40/4 = 10 msec. Delay in first flip flop + delay in second flip flop and so on.

CMOS has the highest delay as compared to devices given in other options.

Yes, all the options 1, 2 and 3 are correct.

NOT gate is also known as inverter as it has a single input with simple behaviour and if the input is true, then the output will be false and vice-versa.

Maskable interrupt (IRQ) is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask.

Maskable interrupt (IRQ) is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask.

This register is used for providing its value for PUSH, POP, CALL and RET instructions.

Yes,  both 0 or 1 are binary digits. These can be understand by the computer.

This instruction provides a means of loading any register pair with a two-byte value.

This instruction allows the programmer to accept input data as BCD, process it in the accumulator using essentially hexadecimal arithmetic, and then convert the result back into BCD.

This instruction provides a means of adding a fixed value into the accumulator.

This instruction provides a 1's complement of the 8-bits in the A register.

This instruction provides a means of subtracting a fixed value into the accumulator.

This instruction set in 8085 architecture permits the HL register pair's contents to be exchanged with the DE pair.