Multiple choice

Directions: Carry Two Marks Each.

A 1-to-8 demultiplexer with data input Din, address inputs S0, S1 and S2 (with S0 as the LSB) and $\overline{y}_o$ to $\overline{y}_7$ as the eight demultiplexed output, is to be designed using two 2 - to - 4 decoders (with enable input $\bar{E}$ and address input A0 and A1). As shown in the figure, Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be

  1. S2, Din, S0 and S1

  2. S1, Din, S0 and S2

  3. Din, S0, S1 and S2

  4. Din, S2, S0 and S1
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D Correct answer
Explanation

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