Computer Knowledge

Digital Logic and Microprocessors

735 Questions

Digital logic and microprocessors form the core of computer science, covering logic gates, combinational and sequential circuits, and CPU architecture. These topics are crucial for computer knowledge sections in technical exams. Test your digital electronics basics here.

Logic gates and circuitsCombinational vs sequential circuitsMicroprocessor instructionsTruth tables and boolean functions

Digital Logic and Microprocessors Questions

Multiple choice

Refer to the NAND and NOR latches shown in the figures. The inputs (P1, P2) for both latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are

  1. NAND : first (0, 1) then (0, 1) NOR : first (1, 0) then (0, 0)

  2. NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0)

  3. NAND : first (1, 0) then (1, 0) NOR : first (0, 1) then race around

  4. NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0, 1)
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

For the NAND latch the transistion as per excitation table will be: 

For the NOR latch the next stable states will be:

  

Multiple choice

Without any additional circuitry, an 8 : 1 MUX can be used to obtain

  1. some but not all Boolean functions of 3 variables

  2. all function of 3 variables but none of 4 variables

  3. all functions of 3 variables and some but not all of 4 variables

  4. all functions of 4 variables
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

A $2^n.1$ MUX can implement all logic functions of (n+1) variable without and y additional circuitry. Here n = 3. Thus a 8:1 MUX can implement all logic functions of 4 variable.

Multiple choice

In the circuit shown in Figure, A is a parallel in, parallel-out 4-bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4-bit bus, W. Its output acts as the input to a 16$\times$4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows:

$$ \begin{array}{c|c} \ Address & 0 & 2 & 4 & 6 & 8 & 10 & 11 & 14 \\ Data & 0011 & 1111 & 0100 & 1010 & 1011 & 1000 & 0010 & 1000 \end{array} $$

The clock to the register is shown, and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is

  1. 1111

  2. 1011

  3. 1000

  4. 0010
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

After $t = t_1$, at first rising edge of clock, the output of shift register is 0110, which in input to address line of ROM. At 0110 is applied to register. So at this time data stored in ROM at 1010 (10), 1000 will be on bus.

When W has the data 0110 and it is 6 in decimal, and it's data value at that add is 1010 then 1010 i.e. 10 is acting as odd, at time $t_2$ and data at that movement is 1000.

Multiple choice

An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the Control register. The address lines A3 to A7 as well as the IO$\sqrt M$signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is

  1. F8H - FBH

  2. F8H - FCH

  3. F8H - FFH

  4. F0H - F7H
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Multiple choice

The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1. The corresponding stable P, Q outputs will be

  1. P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1

  2. P = 1, Q = 0; P = 0, Q = 1; or P = 0, Q = 1; P = 0, Q = 1

  3. P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1

  4. P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation