Multiple choice

In the circuit shown in Figure, A is a parallel in, parallel-out 4-bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4-bit bus, W. Its output acts as the input to a 16$\times$4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows:

$$ \begin{array}{c|c} \ Address & 0 & 2 & 4 & 6 & 8 & 10 & 11 & 14 \\ Data & 0011 & 1111 & 0100 & 1010 & 1011 & 1000 & 0010 & 1000 \end{array} $$

The clock to the register is shown, and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is

  1. 1111

  2. 1011

  3. 1000

  4. 0010
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C Correct answer
Explanation

After $t = t_1$, at first rising edge of clock, the output of shift register is 0110, which in input to address line of ROM. At 0110 is applied to register. So at this time data stored in ROM at 1010 (10), 1000 will be on bus.

When W has the data 0110 and it is 6 in decimal, and it's data value at that add is 1010 then 1010 i.e. 10 is acting as odd, at time $t_2$ and data at that movement is 1000.

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