Digital Logic and Microprocessors

Question 1

Multiple choice

For the circuit shown in figure below, two 4-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full-adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, what will be the outputs of the full-adder?

S = 0, C₀ = 0
S = 0, C₀ = 1
S = 1, C₀ = 0

Reveal answer Fill a bubble to check yourself

Answer

S = 1, C₀ = 1

Question 2

Multiple choice

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q₁ Q₀ sequence 00 ^{_{$\rightarrow$}}01 ^{_{$\rightarrow$}} 11 ^{_{$\rightarrow$}} 10 ^{_{$\rightarrow$}} 00 ^{_{$\rightarrow$}}......... The inputs D₀ and D₁ respectively should be connected as

^{$\bar Q_0$}and Q₁
^{$\bar Q_1$$\bar Q_0$}and ^{$\bar Q_1$} Q₀
^{$\bar Q_1$$\bar Q_0$}and Q₀ Q₁

Reveal answer Fill a bubble to check yourself

Answer

^{$\bar Q_1$}and Q₀

Question 3

Multiple choice

The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns:

(P) (Q) (R) (S) Fanout is minimum DTL DTL TTL CMOS Power consumption is minimum TTL CMOS ECL DTL Propagation delay is minimum CMOS ECL TTL TTL
The correct column is

P
Q
R
S

Reveal answer Fill a bubble to check yourself

Answer

PQ + P$\bar Q$S + $\overline{QRS}$

Answer

Carry flag will be set but Zero flag will be reset

Answer

ADD B, DCR C, JNZ LOOP

Answer

a = $\dfrac{1}{6}$and b = $\dfrac{1}{12}$

Answer

A and F, respectively

Answer

3-input XOR gate

Answer

Input A is connected to ^{$\overline{Q_1}$}

Answer

F = ^{$\overline{X}$}YZ + X^{$\overline{Y}$}Z

Answer

MVI A, 00H LOOP ADD C DCR B JNZ LOOP HLT

Question 4

Multiple choice

For the circuit shown in the following, I₀ - I₃are inputs to the 4 : 1 multiplexers, R (MSB) and S are control bits. The output Z can be represented by

P$\bar Q$ + PQ$\bar R$+ $\overline{PQS}$
P$\overline{QR}$+ $\bar P$QR + PARS + $\overline{QRS}$
PQ$\bar R$+ PQR$\bar S$+ P$\overline{QR}$S + $\overline{QRS}$

Reveal answer Fill a bubble to check yourself

Question 5

Multiple choice

In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result,

Carry flag will be reset but Zero flag will be set
both Carry flag and Zero flag will be reset
both Carry flag and Zero flag will be set

Reveal answer Fill a bubble to check yourself

Question 6

Multiple choice

It is desired to multiply the numbers 0AH by 0BH and store the result in the accumulator. The numbers are available in registers B and C respectively. A part of the 8085 program for this purpose is given below : MVI A, 00H

LOOP ------

HLT END The sequence of instructions to complete the program would be

JNX LOOP, ADD B, DCR C
ADD B, JNZ LOOP, DCR C
DCR C, JNZ LOOP, ADD B

Reveal answer Fill a bubble to check yourself

Question 7

Multiple choice

An input to a 6-level quantizer has the probability density function f(x) as shown in the figure. Decision boundaries of the quantizer are chosen so as to maximize the entropy of the quantizer output. It is given that 3 consecutive decision boundaries are -1, 0 and 1.

The values of a and b are

a = $\dfrac{1}{5}$and b = $\dfrac{3}{40}$
a = $\dfrac{1}{4}$and b = $\dfrac{1}{16}$
a = $\dfrac{1}{3}$and b = $\dfrac{1}{24}$

Reveal answer Fill a bubble to check yourself

Question 8

Multiple choice

The cascode amplifier is a multistage configuration of

CC-CB
CE-CB
CB-CC
CE-CC

Reveal answer Fill a bubble to check yourself

Question 9

Multiple choice

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are

B and F, respectively
H and F, respectively
A and C, respectively

Reveal answer Fill a bubble to check yourself

Question 10

Multiple choice

A 3-input majority gate is defined by the logic function M(a, b, c) = ab + bc + ca. Which of the following gates is represented by the function ^{$M(\overline{M(a, b, c)}, M(a, b, \bar{c}),c)$}?

3-input NAND gate
3-input NOR gate
3-input XNOR gate

Reveal answer Fill a bubble to check yourself

Question 11

Multiple choice

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

01110....
01010....
00110....
01100....

Reveal answer Fill a bubble to check yourself

Question 12

Multiple choice

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI₀- DI₇) from an external device is shown in the figure. The instruction for correct data transfer is

MVI A, F8H
IN F8H
OUT F8H
LDA F8F8H

Reveal answer Fill a bubble to check yourself

Question 13

Multiple choice

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

Input A is connected to ^{$\overline{Q_2}$}
Input A is connected to ^{$\overline{Q_2}$}
Input A is connected to ^{$\overline{Q_1}$} and S is complemented

Reveal answer Fill a bubble to check yourself

Question 14

Multiple choice

The output F in the digital logic circuit shown in the figure is

F = ^{$\overline{X}$}Y^{$\overline{Z}$} + X^{$\overline{YZ}$}
F = ^{$\overline{XY}$}Z + XYZ
F = ^{$\overline{XYZ}$}+ XYZ

Reveal answer Fill a bubble to check yourself

Question 15

Multiple choice

Which of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?

MVI A, 00H JNZ LOOP CMP C LOOP DCR B HLT
MVI A, 00H CMP C LOOP DCR B JNZ LOOP HLT
MVI A, 00H ADD C JNZ LOOP LOOP INR B HLT

Reveal answer Fill a bubble to check yourself

Digital Logic and Microprocessors

Digital Logic and Microprocessors Questions

LOOP ------