Multiple choice

Refer to the NAND and NOR latches shown in the figures. The inputs (P1, P2) for both latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are

  1. NAND : first (0, 1) then (0, 1) NOR : first (1, 0) then (0, 0)

  2. NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0)

  3. NAND : first (1, 0) then (1, 0) NOR : first (0, 1) then race around

  4. NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0, 1)
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C Correct answer
Explanation

For the NAND latch the transistion as per excitation table will be: 

For the NOR latch the next stable states will be:

  

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