Multiple choice

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is Rn <= PC = 1; PC <= M [PC];

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

  1. 2

  2. 3

  3. 4

  4. 5
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B Correct answer
Explanation

Rn $\leftarrow$ PC + 1 PC = M[PC] Program outer is itself a register so incremented in 1 cycle. Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles. So total 1 + 2 = 3 cycles.

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