Consider the following program segment for a hypothetical CPU having three user registers Rl R2 and R3. Instruction Operation Instruction Size in word. MOV Rl,5000 ; Rl ¬ Memory[5000] 2 MOV R2,(R1) ; R2 ¬ Memory[(Rl)] ADD R2,R3 ; R2 ¬ R2 + R3 1 MOV 6000, R2 ; Memory[6000] ¬ R2 2 HALT; Machine halts 1 Let the clock cycles required for various operations be as follows. 1 Register to/from memory transfer : 3 clock cycles ADD with both operands in register: 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is