Consider the following program segment for a hypothetical CPU having three user registers R1,R2 and R3.

Let the clock cycles required for various operations be as follows: ADD with both operands in register: 1 clock cycle Instruction fetch and decode: 2 clock cycles per word Register to/from memory transfer: 3 clock cycles

The total number of clock cycles required to execute the program is

Consider the following program segment for a hypothetical CPU having three user registers R1,R2 and R3.

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

A hard disk with a transfer rate of 10 M bytes/second is constantly transferring data to memory using DMA. The processor runs at 600 MHz. and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes,

What is the percentage of processor time consumed for the transfer operation?

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

What is the swap apace in the disk used for?

Normally user programs are prevented from handing I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction.

Which one of the following is true for a CPU with memory mapped I/O?

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

Match List-I with List-II and select the correct answer using the codes given below the lists:

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 $\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

Consider a disk drive with the following specification 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 n sec. The maximum percentage of time that the CPU gets blocked during DMA operation is

Increasing the RAM of a computer typically improves performance because

A 5 stage pipelined CPU has the following sequence of stages IF-Instruction fetch from instruction memory. RD-Instruction decode and register read, EX- Execute: ALU operation for data and address computation, MA-Data memory access-for write access the register read at RD stage it used, WB-register write back. Consider the following sequence of instruction:

I₁: LR0, Locl; R0 < = M[Locl] I₂ AR0,R0; R0 < = R0 + R0 I₃ AR2,R0; R2 < = R2 − R0

Let each stage take one clock cycle. What is the number of clock cycles taken to complete the above sequence of instruction starting from the fetch of I₁?

Consider a three word machine instruction ADD A[R₀],@ B The first operand (destination) “A[R₀]” uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the op code, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the following is a legal program counter (all values in decimal)?

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is R_n <= PC = 1; PC <= M [PC];

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “add R0,R1” has the register transfer in terpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is 8, 12, 0, 12, 8