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Test 4 - Computer Organization & Architecture | Computer Science

Description: GATE Previous year Topic Wise Questions and Answers | Computer Organization & Architecture
Number of Questions: 19
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Tags: Computer Organization and Architecture GATE CS
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Consider the following program segment for a hypothetical CPU having three user registers R1,R2 and R3.

Let the clock cycles required for various operations be as follows:
ADD with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word
Register to/from memory transfer: 3 clock cycles

The total number of clock cycles required to execute the program is

  1. 29

  2. 24

  3. 23

  4. 20


Correct Option: B
Explanation:

Consider the following program segment for a hypothetical CPU having three user registers R1,R2 and R3.

Consider that the memory is byte addressable with size 32 bits, and
the program has been loaded starting from memory location 1000
(decimal). If an interrupt occurs while the CPU has been halted after
executing the HALT instruction, the return address (in decimal) saved in the stack will be

  1. 1007

  2. 1020

  3. 1024

  4. 1028


Correct Option: D
Explanation:

A hard disk with a transfer rate of 10 M bytes/second is constantly transferring data to memory using DMA. The processor runs at 600 MHz. and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes,

What is the percentage of processor time consumed for the transfer operation?

  1. 5.0%

  2. 1.0%

  3. 0.5%

  4. 0.1%


Correct Option: D
Explanation:

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

  1. 10, 3, 1024

  2. 8, 5, 256

  3. 5, 8, 2048

  4. 10, 3, 512


Correct Option: A
Explanation:

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

  1. 120.4 microseconds

  2. 160.5 microseconds

  3. 165.5 microseconds

  4. 590.0 microseconds


Correct Option: C
Explanation:


What is the swap apace in the disk used for?

  1. Saving temporary html pages

  2. Saving process data

  3. Storing the super-block

  4. Storing device drivers


Correct Option: B
Explanation:

Swap space is the memory pre allowed to store process's data. This can be compared with virtual memory. The data required to complete process is kept here.

Normally user programs are prevented from handing I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction.

Which one of the following is true for a CPU with memory mapped I/O?

  1. I/O protection is ensured by operating system routine(s)

  2. I/O protection is ensured by a hardware trap

  3. I/O protection is ensured during system configuration

  4. I/O protection is not possible


Correct Option: A
Explanation:

In memory mapped I/0 the complete system (memory + I/0 ports) hold the same set of addresses. They are considered to be the part of that memory only. This management is done by OS only.

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

  1. 10,17

  2. 10,22

  3. 15,17

  4. 5,17


Correct Option: A
Explanation:

Match List-I with List-II and select the correct answer using the codes given below the lists:

  1. A - 3, B - 2, C - 1

  2. A - 1, B - 3, C - 2

  3. A - 2, B - 3, C - 1

  4. A - 1, B - 2, C - 3


Correct Option: C
Explanation:

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 $\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

  1. 15

  2. 25

  3. 35

  4. 45


Correct Option: B
Explanation:

Consider a disk drive with the following specification 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 n sec. The maximum percentage of time that the CPU gets blocked during DMA operation is

  1. 10

  2. 25

  3. 40

  4. 50


Correct Option: B
Explanation:

Increasing the RAM of a computer typically improves performance because

  1. Virtual memory increases

  2. Larger RAMs are faster

  3. Fewer page faults occur

  4. Fewer segmentation faults occur


Correct Option: C
Explanation:

Due to increase in RAM size all the pages required by CPU are available in RAM so page fault chance are less, so virtual memory access chances are less and latency is reduced for secondary memory.

A 5 stage pipelined CPU has the following sequence of stages IF-Instruction fetch from instruction memory. RD-Instruction decode and register read, EX- Execute: ALU operation for data and address computation, MA-Data memory access-for write access the register read at RD stage it used, WB-register write back. Consider the following sequence of instruction:

I1: LR0, Locl; R0 < = M[Locl]
I2 AR0,R0; R0 < = R0 + R0
I3 AR2,R0; R2 < = R2 − R0

Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instruction starting from the fetch of I1?

  1. 8

  2. 10

  3. 12

  4. 15


Correct Option: B
Explanation:

Consider a three word machine instruction
ADD A[R0],@ B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the op code, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

  1. 3

  2. 4

  3. 5

  4. 6


Correct Option: D
Explanation:

ADD A[R0],@ B
This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A[R0] here R0 is index register which has starting address of index then this index has the block address. This whole operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So overall 1 + 3 + 2 = 6 machine cycles

A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the following is a legal program counter (all values in decimal)?

  1. 400

  2. 500

  3. 600

  4. 700


Correct Option: C
Explanation:

Size of instruction = 24 bits. Since each instruction require $\dfrac{24}{3}$= 3 bytes & start address is 300 so the address for this range can be multiple of 3 only so 600.

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
Rn <= PC = 1;
PC <= M [PC];

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

  1. 2

  2. 3

  3. 4

  4. 5


Correct Option: B
Explanation:

Rn $\leftarrow$ PC + 1
PC = M[PC]
Program outer is itself a register so incremented in 1 cycle. Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles. So total 1 + 2 = 3 cycles.

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

  1. Neither vectored interrupt nor multiple interrupting devices are possible

  2. Vectored interrupts are not possible but multiple interrupting devices are possible

  3. vectored interrupts and multiple interrupting devices are both possible

  4. vectored interrupt is possible but multiple interrupting devices are not possible


Correct Option: B
Explanation:

Here multiple requests can be given to CPU but CPU interrupts only for highest priority interrupt so option (1) & (4) are wrong. But here in case of single interrupt lines definitely vectored interrupts are not possible.

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “add R0,R1” has the register transfer in terpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is

  1. 2

  2. 3

  3. 4

  4. 5


Correct Option: D
Explanation:

R0 $\leftarrow$ R0+ R1
First cycle require to fetch operands two cycles required for this. The next cycle required to use ALU to perform ADD operation. So total cycles required = 3

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is 8, 12, 0, 12, 8

  1. 2

  2. 4

  3. 3

  4. 5


Correct Option: C
Explanation:


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