A 5 stage pipelined CPU has the following sequence of stages IF-Instruction fetch from instruction memory. RD-Instruction decode and register read, EX- Execute: ALU operation for data and address computation, MA-Data memory access-for write access the register read at RD stage it used, WB-register write back. Consider the following sequence of instruction:

I₁: LR0, Locl; R0 < = M[Locl] I₂ AR0,R0; R0 < = R0 + R0 I₃ AR2,R0; R2 < = R2 − R0

Let each stage take one clock cycle. What is the number of clock cycles taken to complete the above sequence of instruction starting from the fetch of I₁?