Consider an instruction pipeline with five stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, ….. I₁₂ is executed in this pipelined processor. Instruction I₄ is the only branch instruction and its branch target is 9 I₉. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is