Multiple choice

Consider the following data path of a simple non-pipelined CPU. The registers A, B, A1, A2, MDR the bus and the ALU are 8 - bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 x (2 : 1) and the DEMUX is of size 8 x (1 : 2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where A or B, has the specification M [SP] $\leftarrow$r SP $\leftarrow$ SP $\leftarrow$1 How many CPU clock cycles are needed to execute the “push r” instruction?

  1. 2

  2. 3

  3. 4

  4. 5
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

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