0
Alien head

Test 3 - Computer Organization and Architecture | Computer Science

Description: Computer Organization & Architecture Quiz
Number of Questions: 20
Created by:
Tags: Computer Organization and Architecture GATE CS
Attempted 0/20 Correct 0 Score 0

A low memory can be connected to 8085 by using

  1. INTER

  2. RESET IN

  3. HOLD

  4. READY


Correct Option: D
Explanation:

A low memory can be connected to 8085 by using READY signal. If READY is set then communication is possible.

More than one word are put in one cache block to

  1. Exploit the temporal locality of reference in a program

  2. Exploit the spatial locality of reference in a program

  3. Reduce the miss penalty

  4. None of the above


Correct Option: A
Explanation:

Cache is the small memory which has a very less access time. So it is used for temporal locality of reference whereas virtual memory is for spatial locality of reference.

A processor needs software interrupt to

  1. Test the interrupt system of the processor.

  2. Implement co-routines.

  3. Obtain system services which need execution of privileged instructions.

  4. Return from subroutine.


Correct Option: C
Explanation:

A CPU needs software interrupt to obtain system services which need execution of privileged instructions.

Suppose a processor does not have any stack pointer register. Which of the following statements is true?

  1. It cannot have subroutine call instruction.

  2. It can have subroutine call instruction, but no nested subroutine calls.

  3. Nested subroutine calls are possible, but interrupts are not.

  4. All sequences of subroutine calls and also interrupts are possible.


Correct Option: A
Explanation:

Stack pointer register holds the address of top of stack, which is the location of memory at which the CPU should resume its execution after servicing some interrupt or subroutine call. So if SP register not available then no subroutine call instructions are possible.

A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non privileged.

  1. A hardware interrupt is needed.

  2. A software interrupt is needed.

  3. A privileged instruction (which does not generate an interrupt) is needed.

  4. A non-privileged instruction (Which does not generate an interrupt) is needed.


Correct Option: B
Explanation:

A software interrupt is initiated by some program module which needs some CPU services, at that time the two modes can be interchanged.

Which of the following does not interrupt a running process?

  1. A device

  2. Timer

  3. Scheduler process

  4. Power failure


Correct Option: C
Explanation:

A device can request interrupt service. A timer when finishes or power failure causes a running process to stop. But a scheduler process doesn't do this.

Which of the following requires a device driver?

  1. Register

  2. Cache

  3. Main memory

  4. Disk


Correct Option: D
Explanation:

Device driver is the program which co-ordinates with CPU to regulate the devices. Register, cache & main memory are directly connected to CPU. So only Disk from given options require device drivers.

The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called

  1. Assembly

  2. Parsing

  3. Relocation

  4. Symbol resolution


Correct Option: C
Explanation:

Load addresses are assigned to various parts of the program, the program can be loaded at any location in memory. This location is added to all addresses in the code, to get correct references. This makes a code re-locatable.

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

  1. INTA is active

  2. HOLD is active

  3. READY is active

  4. None of the above


Correct Option: A
Explanation:

INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can't be accepted till CPU is busy in servicing interrupt.

In 8085 which of the following modifies the program counter?

  1. Only PCHL instruction

  2. Only ADD instructions

  3. Only JMP and CALL instructions

  4. All instructions


Correct Option: D
Explanation:

Program counter is the register which has the next location of the program to be executed next. JMP & CALL changes the value of PC. PCHL instruction copies content of registers H & L to PC. ADD instruction after completion increments program counter. So program counter is modified in all cases.

Which is the most appropriate match for the items in the first column with the items in the second column?
(X) Indirect Addressing (I) Array implementation
(Y) Indexed Addressing (II) Writing re-locatable code
(Z) Base Register Addressing (III) Passing array as parameter

  1. (X, III) (Y, I) (Z, II)

  2. (X, II) (Y, III) (Z, I)

  3. (X, III) (Y, II) (Z, I)

  4. (X, I) (Y, III) (Z, II)


Correct Option: A
Explanation:

Indexed addressing is used for array implementation where each element has indexes. Base register is used to re-locatable code, where starts from base address & then all local addresses as added to base address. Indirect addressing is done when array is passed as parameter only name is passed.

In the absolute the addressing mode

  1. The operand is inside the instruction

  2. The address of the operand is inside the instruction

  3. The register containing the address of the operand is specified inside the instruction

  4. The location of the operand is implicit


Correct Option: D
Explanation:

In absolute addressing mode, no need of giving operand, the operand are implicit, instruction itself has knowledge of operands.

In serial data transmission, every byte of data is padded with a '0' in the beginning and one or two '1's at the end of byte because

  1. Receiver is to be synchronized for byte reception

  2. Receiver recovers lost '0's and '1' from these padded bits

  3. Padded bits are useful in parity computation.

  4. None of the above


Correct Option: A
Explanation:

In serial data transmission the sender & receiver needs to be synchronized with each other. Receiver should know when 1 byte of data has been sent. 0 & 1's which are padded tell the receiver to synchronize.

Which of the following is not a form of memory?

  1. Instruction cache

  2. Instruction register

  3. Instruction opcode

  4. Translation-a-side buffer


Correct Option: C
Explanation:

Instruction register stores instruction, look-a-side buffer & instruction cache are also memory. But instruction opcodes are the opcodes related to an instruction which are not part of memory hierarchy.

Horizontal microprogramming

  1. Does not require use of signal decoders

  2. Results in larger sized microinstructions than vertical microprogramming

  3. Uses one bit for each control signal

  4. All of the above


Correct Option: C
Explanation:

In horizontal microprogramming the instruction size is not large, & no decoding is required. But 1 bit is used for all control signals.

In the C language

  1. At most one activation record exists between the current activation record and the activation record for the main.

  2. The number of activation records between the current activation record and the activation record for the main depends on the actual function calling sequence.

  3. The visibility of global variables depends on the actual function calling sequence.

  4. Recursion requires the activation record for the recursive function to be saved on a different stack before the recursive fraction can be called.


Correct Option: A
Explanation:

Activation record is the contiguous memory locations where the data needed by the program is kept so at most one activation record exist between current activation record & the record for the main.

The performance of a pipelined processor suffers if

  1. The pipelined stages have different delays

  2. Consecutive instructions are dependent on each other

  3. The pipeline stages share hardware resources

  4. All the above


Correct Option: D
Explanation:

Pipelining is a method to execute a program breaking it in several independent sequence of stages. In that case pipeline stages can't have different delays, no dependency among consecutive instructions & sharing of hardware resources shouldn't be there. So option (4) is true

Which of the following addressing modes are suitable for program relocation at run time?

  1. Absolute addressing
  2. Based addressing
  3. Relative addressing
  4. Indirect addressing
  1. 1 and 4

  2. 1 and 2

  3. 2 and 3

  4. 1, 2 and 4


Correct Option: C
Explanation:

Program relocation at run time transfers complete block to some memory locations. This require as base address and block should be relatively addressed through this base address. This require both based addressing and relative addressing mode.

Consider the following data path of a simple non-pipelined CPU. The registers A, B, A1, A2, MDR the bus and the ALU are 8 - bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 x (2 : 1) and the DEMUX is of size 8 x (1 : 2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.


The CPU instruction “push r”, where A or B, has the specification
M [SP] $\leftarrow$r
SP $\leftarrow$ SP $\leftarrow$1
How many CPU clock cycles are needed to execute the “push r” instruction?

  1. 2

  2. 3

  3. 4

  4. 5


Correct Option: B
Explanation:

Consider a multiplexer with X and Y as data inputs and Z as control input's = 0 selects input X, and Z = 1 selects input Y. What are the connection required to realize the 2 - variable Boolean function f = T + R, without using any additional hardware?

  1. R to X, 1 to Y, T to Z

  2. T to X, R to Y, T to Z

  3. T to X, R to Y, 0 to Z

  4. R to X, 0 to Y, T to Z


Correct Option: A
Explanation:

+ View questions