Test 3 - Computer Organization and Architecture | Computer Science
Computer Organization & Architecture Quiz
Questions
A low memory can be connected to 8085 by using
- INTER
- RESET IN
- HOLD
- READY
More than one word are put in one cache block to
- Exploit the temporal locality of reference in a program
- Exploit the spatial locality of reference in a program
- Reduce the miss penalty
- None of the above
A processor needs software interrupt to
- Test the interrupt system of the processor.
- Implement co-routines.
- Obtain system services which need execution of privileged instructions.
- Return from subroutine.
Suppose a processor does not have any stack pointer register. Which of the following statements is true?
- It cannot have subroutine call instruction.
- It can have subroutine call instruction, but no nested subroutine calls.
- Nested subroutine calls are possible, but interrupts are not.
- All sequences of subroutine calls and also interrupts are possible.
A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non privileged.
- A hardware interrupt is needed.
- A software interrupt is needed.
- A privileged instruction (which does not generate an interrupt) is needed.
- A non-privileged instruction (Which does not generate an interrupt) is needed.
Which of the following does not interrupt a running process?
- A device
- Timer
- Scheduler process
- Power failure
Which of the following requires a device driver?
- Register
- Cache
- Main memory
- Disk
The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called
- Assembly
- Parsing
- Relocation
- Symbol resolution
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
- INTA is active
- HOLD is active
- READY is active
- None of the above
In 8085 which of the following modifies the program counter?
- Only PCHL instruction
- Only ADD instructions
- Only JMP and CALL instructions
- All instructions
Which is the most appropriate match for the items in the first column with the items in the second column?
(X) Indirect Addressing (I) Array implementation
(Y) Indexed Addressing (II) Writing re-locatable code
(Z) Base Register Addressing (III) Passing array as parameter
- (X, III) (Y, I) (Z, II)
- (X, II) (Y, III) (Z, I)
- (X, III) (Y, II) (Z, I)
- (X, I) (Y, III) (Z, II)
In the absolute the addressing mode
- The operand is inside the instruction
- The address of the operand is inside the instruction
- The register containing the address of the operand is specified inside the instruction
- The location of the operand is implicit
In serial data transmission, every byte of data is padded with a '0' in the beginning and one or two '1's at the end of byte because
- Receiver is to be synchronized for byte reception
- Receiver recovers lost '0's and '1' from these padded bits
- Padded bits are useful in parity computation.
- None of the above
Which of the following is not a form of memory?
- Instruction cache
- Instruction register
- Instruction opcode
- Translation-a-side buffer
Horizontal microprogramming
- Does not require use of signal decoders
- Results in larger sized microinstructions than vertical microprogramming
- Uses one bit for each control signal
- All of the above
In the C language
- At most one activation record exists between the current activation record and the activation record for the main.
- The number of activation records between the current activation record and the activation record for the main depends on the actual function calling sequence.
- The visibility of global variables depends on the actual function calling sequence.
- Recursion requires the activation record for the recursive function to be saved on a different stack before the recursive fraction can be called.
The performance of a pipelined processor suffers if
- The pipelined stages have different delays
- Consecutive instructions are dependent on each other
- The pipeline stages share hardware resources
- All the above
Which of the following addressing modes are suitable for program relocation at run time?
- Absolute addressing
- Based addressing
- Relative addressing
- Indirect addressing
- 1 and 4
- 1 and 2
- 2 and 3
- 1, 2 and 4
Consider the following data path of a simple non-pipelined CPU. The registers A, B, A1, A2, MDR the bus and the ALU are 8 - bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 x (2 : 1) and the DEMUX is of size 8 x (1 : 2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.
The CPU instruction “push r”, where A or B, has the specification
M [SP] $\leftarrow$r
SP $\leftarrow$ SP $\leftarrow$1
How many CPU clock cycles are needed to execute the “push r” instruction?
- 2
- 3
- 4
- 5
Consider a multiplexer with X and Y as data inputs and Z as control input's = 0 selects input X, and Z = 1 selects input Y. What are the connection required to realize the 2 - variable Boolean function f = T + R, without using any additional hardware?
- R to X, 1 to Y, T to Z
- T to X, R to Y, T to Z
- T to X, R to Y, 0 to Z
- R to X, 0 to Y, T to Z
