Digital Logic and Microprocessors

Here, the output is false only when both the inputs are true.

The mode control, which may be multiple inputs, controls parallel loading vs shifting.

The output is true only when any one of the inputs were true and output is false if both inputs are at the same logic.

The output is true only when both the inputs are false.

These instructions can specify the address of the next instruction to be executed, if it is not the one immediately following the branch , in two ways in 8085 processor.

The outputs is true only when both the inputs were either true or false.

Yes, all the three are false statements.

If ∆₀ < P, the fourth electron will go to higher energy e_g orbital. Thus, this option is correct.

The accumulator is a register in the Arithmetic Logic Unit (ALU) where intermediate arithmetic and logic results are stored. The ALU performs mathematical and logical operations, and the accumulator is central to this process. Input, output, and control units are separate components of the computer architecture.

CPU clock speed measures how many instruction cycles the processor can execute per second, measured in Hertz (Hz). Modern processors operate in gigahertz (GHz) range, meaning billions of cycles per second, which determines how quickly the CPU can process instructions.

FLOPS (Floating Point Operations Per Second) measures computer performance in powers of 1000. Both megaFLOPS (10^6 operations/sec) and gigaFLOPS (10^9 operations/sec) are standard units, making option D correct. TeraFLOPS (10^12) is also valid but the question asks which pair is correct, and A-B are indeed real FLOPS types.

Parallel adders use combinational logic - they compute sums instantly based solely on current inputs without any memory elements. All full-adder circuits operate simultaneously on all bit positions, hence 'parallel'. Sequential circuits require memory and clock signals, which parallel adders do not use. They are purely feedforward logic networks.

When constructing a JK flip-flop from an SR flip-flop, we need to prevent the invalid state (S=1, R=1) and enable toggling (J=1, K=1). The correct mapping is S = JQ' and R = KQ. When Q=0, S=J and R=0, so setting J=1 sets Q to 1. When Q=1, S=0 and R=K, so setting K=1 resets Q to 0. When J=K=1 and Q=0, the SR inputs become (1,0) setting Q to 1; when Q=1, they become (0,1) resetting Q to 0 - thus toggling.

In an RS flip-flop with both inputs initially at 0 (hold state), applying a momentary 1 to the Set (S) input causes the Q output to become 1 and remain at 1 even after S returns to 0. The flip-flop 'remembers' this state. Option A correctly describes Q flipping from 0 to 1. The other options are incorrect: the output doesn't flip back automatically, doesn't go from 1 to 0, and the behavior is well-defined.

In positive logic, high voltage (1) represents TRUE and low voltage (0) represents FALSE. In negative logic, this is inverted: high voltage (1) represents FALSE and low voltage (0) represents TRUE. An AND gate in positive logic (Y = A AND B) becomes an OR gate in negative logic because the voltage levels that indicate TRUE are swapped. By De Morgan's laws, NOT(NOT(A) AND NOT(B)) = A OR B, confirming this equivalence.