Computer Knowledge

Computer Memory and Storage

2,477 Questions

Computer memory and storage questions test foundational knowledge of hardware, cache mapping, and data transfer mechanisms. Key areas include Direct Memory Access, analog recording, and RAID levels. This section is essential for candidates preparing for banking and government computer proficiency tests.

Cache memory mappingDirect memory accessRAID storage levelsHard disk technologyOptical media storageMemory addresses

Computer Memory and Storage Questions

Multiple choice technology

which of the following statement is true?

  1. indirect function is like a pointer, which returns the value of its address

  2. indirect function indirectly refers the CPU memmory

  3. Indirect function directly referes the CPU memmory

  4. Indirect function refers the CPU and Server Memmory
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

The INDIRECT function returns the value specified by a reference string, acting like a pointer to a cell address. For example, INDIRECT("A1") returns the value in cell A1. Options B, C, and D incorrectly mention CPU memory - INDIRECT works with spreadsheet cell references, not system memory.

Multiple choice technology mainframe

What are the various types of VSAM Data Organizations available?

  1. PSDS, KADS, RRDS, VRRDS, LRDS

  2. ESDS, KSDS, RRDS, VRRDS, LDS

  3. ESDS, KRDS, RRDS, VLDS, VKDS

  4. PSDS, RKDS, KSDS, FRDS, LLDS
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

VSAM datasets support five types of organizations: Entry Sequenced (ESDS), Key Sequenced (KSDS), Relative Record (RRDS), Variable-length Relative Record (VRRDS), and Linear Data Sets (LDS). Other options are incorrect because they introduce invalid abbreviations such as PSDS, KADS, or LLDS, which do not exist in VSAM storage systems.

Multiple choice

No permission is needed to store data in

  1. shared preferences

  2. internal storage

  3. external storage

  4. Both (1) and (2)
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

SharedPreferences and internal storage are private to each application and reside in the app's sandbox, so they require no special permissions. External storage does require permissions (though the exact permissions have changed across Android versions - WRITE_EXTERNAL_STORAGE, READ_EXTERNAL_STORAGE, or scoped storage in newer APIs).

Multiple choice

getExternalStorageDirectory()method returns sdcard location that

  1. is same for all devices

  2. may vary for different devices

  3. is Mnt/sdcard

  4. None of these
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

The external storage directory path varies across devices - different manufacturers use different mount points (e.g., /mnt/sdcard, /sdcard, /storage/emulated/0). Developers should never hardcode paths and should always use the Environment.getExternalStorageDirectory() API or the Storage Access Framework for compatibility.

Multiple choice

________ Permission is required to access external storage.

  1. WRITE_EXTERNAL_STORAGE

  2. READ_EXTERNAL_STORAGE

  3. Both Op1 and Op2

  4. As per requirement, any of Op1 or Op2
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Pre-API 19, WRITE_EXTERNAL_STORAGE alone allowed both read and write. From API 19+, reading doesn't need permission. From API 23+, write permission requires runtime request. The correct answer depends on API level and use case - you may need either one or both depending on operation and Android version.

Multiple choice

In a system with 32 bit virtual addresses and 1KB page size, use of one-level page tables for virtual to physical address translation is not practical because of

  1. the large amount of internal fragmentation

  2. the large amount of external fragmentation

  3. the large memory overhead in maintaining page tables

  4. the large computation overhead in the translation process
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

32 bit virtual address, i.e. $2^{32}$ kB of virtual memory & 1 kB page size. So total pages = $2^{32}$ So. we need to maintain a page table of $2^{32}$ rows, this require 4 GB main memory which is quite impractical due to large memory overhead

Multiple choice

In a system with 32 bit virtual addresses and 1KB page size, use of one-level page tables for virtual to physical address translation is not practical because of

  1. the large amount of internal fragmentation

  2. the large amount of external fragmentation

  3. the large memory overhead in maintaining page tables

  4. the large computation overhead in the translation process
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

32 bit virtual address, i.e. $2^{32}$ kB of virtual memory & 1 kB page size. So total pages = $2^{32}$ So. we need to maintain a page table of $2^{32}$ rows, this require 4 GB main memory which is quite impractical due to large memory overhead

Multiple choice

Using a larger block size in a fixed block size file system leads to

  1. better disk throughput but poorer disk space utilization

  2. better disk throughput and better disk space utilization

  3. poorer disk throughput but better disk space utilization

  4. poorer disk throughput and poorer disk space utilization
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Using larger block size in a fixed block size system lead to poor disk space utilization due to data items which are very small comparable to block size cause fragmentation. But it leads to better disk through put since no. of blocks needs to fetch & replace become less.

Multiple choice

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page.Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

  1. 1.5 ns

  2. 2 ns

  3. 3 ns

  4. 4 ns
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Multiple choice

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page.Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 0×00400000, and a stack page starting at virtual address 0×FFFFF000. The amount of memory required for storing the page tables of this process is

  1. 8 KB

  2. 12 KB

  3. 16 KB

  4. 20 KB
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Multiple choice

A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?

  1. Efficient implementation of multi-user support is no longer possible

  2. The processor cache organization can be made more efficient now

  3. Hardware support for memory management is no longer needed

  4. CPU scheduling can be made more efficient now
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Multiple choice

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two dimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1: for (i=0; i<512; i++) { for (j=0; j<512; j++) { x +=A[i] [j]; } } P2: for (i=0; i<512; i++) { for (j=0; j<512; j++) { x +=A[j] [i]; } } P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 .

The value of 1 M is:

  1. 0

  2. 2048

  3. 16384

  4. 262144
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Multiple choice

A virtual memory system uses First In First Out (FIFO) page replacement policy and allocates a fixed number of frames to a process. Consider the following statements: P: Increasing the number of page frames allocated to a process sometimes increases the page fault rate. Q: Some programs do not exhibit locality of reference. Which one of the following is TRUE?

  1. Both P and Q are true, and Q is the reason for P

  2. Both P and Q are true, but Q is not the reason for P.

  3. P is false, but Q is true

  4. Both P and Q are false.
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation