Computer Knowledge

Computer Memory and Storage

2,121 Questions

Computer memory and storage questions test foundational knowledge of hardware, cache mapping, and data transfer mechanisms. Key areas include Direct Memory Access, analog recording, and RAID levels. This section is essential for candidates preparing for banking and government computer proficiency tests.

Cache memory mappingDirect memory accessRAID storage levelsHard disk technologyOptical media storageMemory addresses

Computer Memory and Storage Questions

Multiple choice
  1. Register Addressing Mode

  2. Register Relative Addressing Mode

  3. Based Index Addressing Mode

  4. Immediate Addressing Mode

  5. Operand

Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

The effective address is the sum of an 8 or 16 bit displacement and the contents of a base register or an index register in 8086 processor.

Multiple choice
  1. Register Addressing Mode

  2. Direct Addressing Mode

  3. Register Indirect Addressing Mode

  4. Instruction Register

  5. Register Selector

Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

The effective address of the datum is in the base register or an index register that is specified by the instruction in 8086 processor.

Multiple choice
  1. Register Mode

  2. Register Indirect Mode

  3. Register Indirect Branch Mode

  4. Direct Mode

  5. Operand

Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

This mode creates three byte long instructions and first byte contains the operation to be performed and second and third bytes contain the address in memory in 8085 processor.

Multiple choice
  1. Shared memory

  2. Message passing model

  3. Both (1) and (2)

  4. All of these

  5. None of these

Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

In the shared-memory programming model, tasks share a common address space, which they read and write asynchronously. So here there is no kernel intervention unlike Message passing model, where message are send and recieve via kernel only.