Computer Knowledge

Computer Memory and Storage

2,477 Questions

Computer memory and storage questions test foundational knowledge of hardware, cache mapping, and data transfer mechanisms. Key areas include Direct Memory Access, analog recording, and RAID levels. This section is essential for candidates preparing for banking and government computer proficiency tests.

Cache memory mappingDirect memory accessRAID storage levelsHard disk technologyOptical media storageMemory addresses

Computer Memory and Storage Questions

Multiple choice

Increasing the RAM of a computer typically improves performance because

  1. Virtual memory increases

  2. Larger RAMs are faster

  3. Fewer page faults occur

  4. Fewer segmentation faults occur
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Due to increase in RAM size all the pages required by CPU are available in RAM so page fault chance are less, so virtual memory access chances are less and latency is reduced for secondary memory.

Multiple choice

A 5 stage pipelined CPU has the following sequence of stages IF-Instruction fetch from instruction memory. RD-Instruction decode and register read, EX- Execute: ALU operation for data and address computation, MA-Data memory access-for write access the register read at RD stage it used, WB-register write back. Consider the following sequence of instruction:

I1: LR0, Locl; R0 < = M[Locl] I2 AR0,R0; R0 < = R0 + R0 I3 AR2,R0; R2 < = R2 − R0

Let each stage take one clock cycle. What is the number of clock cycles taken to complete the above sequence of instruction starting from the fetch of I1?

  1. 8

  2. 10

  3. 12

  4. 15
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Multiple choice

Consider a three word machine instruction ADD A[R0],@ B The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the op code, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

  1. 3

  2. 4

  3. 5

  4. 6
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

ADD A[R0],@ B This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A[R0] here R0 is index register which has starting address of index then this index has the block address. This whole operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So overall 1 + 3 + 2 = 6 machine cycles

Multiple choice

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is Rn <= PC = 1; PC <= M [PC];

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

  1. 2

  2. 3

  3. 4

  4. 5
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Rn $\leftarrow$ PC + 1 PC = M[PC] Program outer is itself a register so incremented in 1 cycle. Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles. So total 1 + 2 = 3 cycles.

Multiple choice

Consider the following data path of a CPU

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation-the first one for loading data from the memory but into the MDR.

The instruction “add R0,R1” has the register transfer in terpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is

  1. 2

  2. 3

  3. 4

  4. 5
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

R0 $\leftarrow$ R0+ R1 First cycle require to fetch operands two cycles required for this. The next cycle required to use ALU to perform ADD operation. So total cycles required = 3

Multiple choice

Which of the following statements is false?

  1. Virtual memory implements the translation of a program's address space into physical memory address space.

  2. Virtual memory allows each program to exceed the size of the primary memory.

  3. Virtual memory increases the degree of multi-programming

  4. Virtual memory reduces the context switching overhead.
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Virtual memory enables a program to exceed the size of primary memory so it increases degree of multi-programming. Since data required by executing program is available here so context switching is reduced. But virtual memory doesn't translate program's address space into physical memory.

Multiple choice

Consider a virtual memory system with FIFO page replacement policy. For an arbitrary page access pattern, increasing the number of page frames in main memory will

  1. always decrease the number of page faults

  2. always increase the number of page faults

  3. sometimes increase the number of page faults

  4. never affect the number of page faults
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

During F1F0 page replacement policy, due to increase in the no. of page frames in memory should decrease the no. of page faults since more frames can be kept there. But due to Belady's Anomaly after certain limit or in some page access instances no. of page faults are high.

Multiple choice

Where does the swap space reside?

  1. RAM

  2. Disk

  3. ROM

  4. On-chip cache
Reveal answer Fill a bubble to check yourself
B Correct answer
Explanation

Swap space is the memory space where the part of the program not currently in main memory for execution is stored, this program part can be swapped into memory when required. This space is generally in disk.

Multiple choice

In a system with 32 bit virtual addresses and 1KB page size, use of one-level page tables for virtual to physical address translation is not practical because of

  1. the large amount of internal fragmentation

  2. the large amount of external fragmentation

  3. the large memory overhead in maintaining page tables

  4. the large computation overhead in the translation process
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

32 bit virtual address, i.e. $2^{32}$ kB of virtual memory & 1 kB page size. So total pages = $2^{32}$ So. we need to maintain a page table of $2^{32}$ rows, this require 4 GB main memory which is quite impractical due to large memory overhead

Multiple choice

Using a larger block size in a fixed block size file system leads to

  1. better disk throughput but poorer disk space utilization

  2. better disk throughput and better disk space utilization

  3. poorer disk throughput but better disk space utilization

  4. poorer disk throughput and poorer disk space utilization
Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

Using larger block size in a fixed block size system lead to poor disk space utilization due to data items which are very small comparable to block size cause fragmentation. But it leads to better disk through put since no. of blocks needs to fetch & replace become less.

Multiple choice

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page.Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

  1. 1.5 ns

  2. 2 ns

  3. 3 ns

  4. 4 ns
Reveal answer Fill a bubble to check yourself
D Correct answer
Explanation

Multiple choice

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page.Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 0×00400000, and a stack page starting at virtual address 0×FFFFF000. The amount of memory required for storing the page tables of this process is

  1. 8 KB

  2. 12 KB

  3. 16 KB

  4. 20 KB
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Multiple choice

A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?

  1. Efficient implementation of multi-user support is no longer possible

  2. The processor cache organization can be made more efficient now

  3. Hardware support for memory management is no longer needed

  4. CPU scheduling can be made more efficient now
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation