Multiple choice

In which, a latching circuit timed with the clock signal would most likely have to be connected to the IGFET gate to ensure full discharge of the capacitor when the comparator's output goes high?

  1. R-2R Ladder DAC

  2. Flash Type ADC

  3. Single Slope Integrating ADC

  4. Tracking Converter

  5. Half Subtractor
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

Here, a latching circuit timed with the clock signal would most likely have to be connected to the IGFET gate to ensure full discharge of the capacitor when the comparator's output goes high.

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