Multiple choice

The circuit shown below consists of JK flip-flops, each with an active low asynchronous reset ($\bar{R}_d$ input). The counter corresponding to this circuit is

  1. a modulo-5 binary up counter

  2. a modulo-6 binary down counter

  3. a modulo-5 binary down counter

  4. a modulo-6 binary up counter
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A Correct answer
Explanation

From the figure, it can be seen that it is a basic modulo UP counter configuration because clock is negative edge triggering at modulo-5.

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