Multiple choice

The figure the internal schematic of a TTL AND-OR-OR-Invert (AOI) gate. For the inputs shown in the figure, the output Y is

  1. 0

  2. 1

  3. AB
  4. $\overline{AB}$
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A Correct answer
Explanation

For the TTL family if terminal is floating, then it is at logic 1. Thus  Y = ($\overline{AB + 1}$) = $\overline{AB}0$= 0

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