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Test 1 - Digital Circuits | Electronics and Communication (ECE)

Topic wise test for Digital Circuits of Electronics and Communication (ECE)

25 Questions Published
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Questions

Question 1 Multiple Choice (Single Answer)

Consider the given circuit.

In this circuit, the race around

  1. does not occur
  2. occurs when CLK = 0
  3. occurs when CLK = 1 and A = B = 1
  4. occurs when CLK = 1 and A = B = 0
Question 2 Multiple Choice (Single Answer)

When the output Y in the circuit below is ‘1’, it implies that data has

  1. changed from 0 to 1
  2. changed from 1 to 0
  3. changed in either direction
  4. not changed
Question 3 Multiple Choice (Single Answer)

Assuming that flip-flops are in reset condition initially, the count sequence observed at QA in the circuit shown is

  1. 0010111…
  2. 0001011…
  3. 0101111…
  4. 01101..........…
Question 4 Multiple Choice (Single Answer)

The two numbers represented in signed 2s complement form are P + 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2s complement is

  1. 1000001111
  2. 00000111
  3. 11111001
  4. 111111001
Question 5 Multiple Choice (Single Answer)

The Boolean function f implemented in figure using two input multiplexers is

  1. $A\bar BC + AB\bar C$
  2. $ABC + A\bar B\bar C$
  3. $\bar ABC + \bar A\bar B\bar C$
  4. $\bar A\bar BC + \bar AB\bar C$
Question 6 Multiple Choice (Single Answer)

The point P in the following figure is stuck-at-1. The output f will be

  1. $\overline{AB\bar C}$
  2. $\bar A$
  3. AB$\bar C$
  4. A
Question 7 Multiple Choice (Single Answer)

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

  1. R = 10 ns, S = 40 ns
  2. R = 40 ns, S = 10 ns
  3. R = 10 ns, S = 30 ns
  4. R = 30 ns, S = 10 ns
Question 8 Multiple Choice (Single Answer)

The minimum number of 2- to -1 multiplexers required to realize a 4- to -1 multiplexers is

  1. 1
  2. 2
  3. 3
  4. 4
Question 9 Multiple Choice (Single Answer)

In the circuit shown

  1. Y = $\bar A\bar B + \bar C$
  2. Y = (A +B)
  3. Y = $(\bar A + \bar B) \bar C$
  4. Y = AB + C
Question 10 Multiple Choice (Single Answer)

The logic function implemented by the circuit below is (ground implies logic 0)

  1. F = AND (P,Q)
  2. F = OR (P,R)
  3. F = OR (P,Q)
  4. F = XOR (P,Q
Question 11 Multiple Choice (Single Answer)

The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required is

  1. 2
  2. 3
  3. 4
  4. 5
Question 12 Multiple Choice (Single Answer)

Directions : Two products are sold from a vending machine, which has two push buttons P1 and P2.
When a button is pressed, the price of the corresponding product is displayed in a 7 - segment display. If no
buttons are pressed, '0' is displayed signifying 'Rs 0'.
If only P1 is pressed, '2' is displayed, signifying 'Rs. 2'.
If only P2 is pressed, '5' is displayed, signifying 'Rs. 5'.
If both P1 and P2 are pressed, 'E' is displayed, signifying 'Error'
The names of the segments in the 7 - segment display, and the glow of the display for '0', '2', '5' and 'E' are shown below.

Consider
(1) push buttons pressed/not pressed in equivalent to logic 1/0 respectively.
(2) a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.

What are the minimum numbers of NOT gates and 2 - input OR gates required to design the logic of the driver for this 7 - Segment display?

  1. 3 NOT and 4 OR
  2. 2 NOT and 4 OR
  3. 1 NOT and 3 OR
  4. 2 NOT and 3 OR
Question 13 Multiple Choice (Single Answer)

The figure the internal schematic of a TTL AND-OR-OR-Invert (AOI) gate. For the inputs shown in the figure, the output Y is

  1. 0
  2. 1
  3. AB
  4. $\overline{AB}$
Question 14 Multiple Choice (Single Answer)

The output of the 74 series of TTL gates is taken from a BJT in

  1. totem pole and common collector configuration
  2. either totem pole or open collector configuration
  3. common base configuration
  4. common collector configuration
Question 15 Multiple Choice (Single Answer)

If X = 1 in logic equation $[X+Z{\bar Y+(\bar Z + X \bar Y ) }] \ [\bar X + \bar Z(X+Y)]$ = 1 then

  1. Y = Z
  2. Y = $\bar Z$
  3. Z = 1
  4. Z = 0
Question 16 Multiple Choice (Single Answer)

A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5 number 24 will be represented by its BCP code 010100. In this numbering system, the BCP code 100010011001 corresponds to the following number in base-5 system

  1. 423
  2. 1324
  3. 2201
  4. 4231
Question 17 Multiple Choice (Single Answer)

Directions : Two products are sold from a vending machine, which has two push buttons P1 and P2.
When a button is pressed, the price of the corresponding product is displayed in a 7 - segment display. If no
buttons are pressed, '0' is displayed signifying 'Rs 0'.
If only P1 is pressed, '2' is displayed, signifying 'Rs. 2'
If only P2 is pressed '5' is displayed, signifying 'Rs. 5'
If both P1 and P2 are pressed, 'E' is displayed, signifying 'Error'
The names of the segments in the 7 - segment display, and the glow of the display
for '0', '2', '5' and 'E' are shown below.

Consider
(1) push buttons pressed/not pressed in equivalent to logic 1/0 respectively.
(2) a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.

If segments a to g are considered as functions of P1 and P2, which of the following is correct?

  1. g = $\overline P_1$+ P2, d = c + e
  2. g = P1+ P2, d = c + e
  3. g = $\overline P_1$+ P2, e = b + c
  4. g = P1+ P2, e = b + c
Question 18 Multiple Choice (Single Answer)

An 8085 assembly language program is given below.
Line 1: MVI A, B5H
2: MVI B, 0EH
3: XRI 69H
4: ADD B
5: ANI 9BH
6: CPI 9FH
7: STA 3010H
8: HLT

The contents of the accumulator just after execution of the ADD instruction in line 4 will be

  1. C3H
  2. EAH
  3. DCH
  4. 69H
Question 19 Multiple Choice (Single Answer)

An 8085 assembly language program is given below.
Line 1: MVI A, B5H
2: MVI B, 0EH
3: XRI 69H
4: ADD B
5: ANI 9BH
6: CPI 9FH
7: STA 3010H
8: HLT

After execution of line 7 of the program, the status of the CY and Z flags will be

  1. CY = 0, Z = 0
  2. CY = 0, Z = 1
  3. CY = 1, Z = 0
  4. CY = 1, Z = 1
Question 20 Multiple Choice (Single Answer)

The transistors used in a portion of the TTL gate shown in figure have $\beta$ = 100 ,the base-emitter voltage is 0.7 V for a transistor in active region and 0.75 V for a transistor in saturation. If the sink current I = 1 mA and the output is at logic 0, then the current IR will be equal to

  1. 0.65 mA
  2. 0.70 mA
  3. 0.75 mA
  4. 1.00 mA
Question 21 Multiple Choice (Single Answer)

Two D flip-flops are connected as a synchronous counter that goes through the following QBQA sequence 00$\rightarrow$11$\rightarrow$01$\rightarrow$10$\rightarrow$00$\rightarrow$…
The combination to the inputs DA and DB are

  1. DA = QB ; DB = QA
  2. DA = $\overline Q_A$; DB = $\overline Q_B$
  3. DA = $(Q_A \bar Q_B + \bar Q_A Q_B)$; DB = $\bar Q_A$
  4. DA = $(Q_A Q_B + \overline {Q_A Q_B})$; DB = $\overline Q_B$
Question 22 Multiple Choice (Single Answer)

In the sum of products function f(X, Y, Z) = $\sum (2,3,4,5)$, the prime implicants are

  1. $\bar XY, X\bar Y$
  2. $\bar XY, X\bar Y \bar Z, X\bar YZ$
  3. $\bar XY\bar Z, \bar XYZ, X\bar Y$
  4. $\bar XY\bar Z, \bar XYZ, X\overline {YZ}, X\bar YZ$
Question 23 Multiple Choice (Single Answer)

The state transition diagram for the logic circuit shown is

Question 24 Multiple Choice (Single Answer)

The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
Y = P $\oplus$Q $\oplus$R
Z = RQ + $\bar P R + Q\bar P$

The circuit acts as a

  1. 4 bit adder giving P + Q
  2. 4 bit subtractor-giving P - Q
  3. 4 bit subtractor-giving Q - P
  4. 4 bit adder giving P + Q + R
Question 25 Multiple Choice (Single Answer)

In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupt is

  1. non-maskable and non-vectored
  2. maskable and non-vectored
  3. non-maskable and vectored
  4. maskable and vectored
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