Multiple choice

Consider a three word machine instruction ADD A[R0],@ B The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the op code, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

  1. 3

  2. 4

  3. 5

  4. 6
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D Correct answer
Explanation

ADD A[R0],@ B This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A[R0] here R0 is index register which has starting address of index then this index has the block address. This whole operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So overall 1 + 3 + 2 = 6 machine cycles

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