Delayed branching can help in the handling of control hazards

The following code is to run on a pipelined processor with one branch delay slot: 11 : ADD R2 ^{_$\leftarrow$} R7 + R8 12 : SUB R4 ^{_$\leftarrow$} R5 – R6 13 : ADD R1 ^{_$\leftarrow$} R2 + R3 14 : STORE Memory [R4] ^{_$\leftarrow$} R1 BRANCH to Label if R1 == 0 Which of the instructions 11, 12, 13 or 14 can legitimately occupy the delay slot without any other program modification?