Multiple choice technology embedded technologies

Hardware test at SPU and SPM restart is provided for boards SPB21,SPb3

  1. All SPM SDRAM tested

  2. The cache memory is enabled during all other tests and thus indirectly tested

  3. both a and b

  4. Ethernet communication controller

  5. both a and d
Reveal answer Fill a bubble to check yourself
C Correct answer
Explanation

For SPB21 and SPb3 boards, hardware tests at SPU and SPM restart cover testing all SPM SDRAM, and the cache memory is enabled during other tests to be tested indirectly. Thus, 'both a and b' is correct, whereas the Ethernet controller test is not the primary combined option.

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