Tag: mainframe

It specifies the initial contents of a data item or the values associated with a condition-name.

It specifies the data item location.

It describes the picture clause.

All of the above

2

4

6

8

R1 will hold 2 and condition code is set to 0

R1 will hold 87, Data1 will hold 85 and condition code is set to 2.

Data1 will hold 87, R1 will hold 2 and condition code is set to 2.

None of the above

The address of the next sequential instruction (NSI) is placed in the 1st-operand register. Subsequently a branch is made to the location given by a 2nd-operand label.

The address of the next sequential instruction (NSI) is placed in the 2nd-operand register. Subsequently a branch is made to the location given by a 1st-operand label.

BAS instruction is not there in Assembler

None of the above

ADDR1 will execute until R2 becomes 0.

ADDR1 will execute until R2 becomes 8.

ADDR1 will never be executed.

All of the above.

The data of the 1st-operand register is compared with the data of the 2nd-operand field. The result of the comparison is indicated in the condition code which may be checked further.

The data of the 1st-operand register is compared with the data of the 2nd-operand field. The result of the comparison is indicated in the condition code which will not be checked further.

The data of the 1st-operand register is compared with the data of the 2nd-operand field. Condition codes are not at all checked.

None of the above.

The quotient is placed in the 1st-operand odd-register and the remainder in the even-register.

The remainder is placed in the 1st-operand odd-register and the quotient in the even-register.

Both are stored in even register.

Both are stored in odd register

DC

DS

No Such Instruction Exists

1 and 2

DS

DC

No such instruction exists.

Both 1 and 2

MYFILE.LIB.TEST.G001

MYFILE.LIB.TEST.G0001V00

MYFILE.LIB.TEST1

WE CANNOT DETERMINE