2003|Electronics and Comm (GATE Exam)-Previous Question Paper Solution

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Question 1 of 90

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

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R = 10 ns, S = 40 ns

R = 40 ns, S = 10 ns

R = 10 ns, S = 30 ns

R = 30 ns, S = 10 ns

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