Test 4 - Electronic Devices | Electronics and Communication (ECE)
Topic wise test for Electronic Devices of Electronics and Communication (ECE)
Questions
If P is Passivation, Q is n-well implant, R is metallization and S is soruce/drain diffusion, then the order in which they are carried out in a standard n-well CMOS fabrication process, is
- P-Q-R-S
- Q-S-R-P
- R-P-S-Q
- S-R-Q-P
At 300 K, for a diode current of 1 mA, a certain germanium diode requires a forward bias of 0.1435V, whereas a certain silicon diode requires a forward bias of 0.718 V. Under the conditions stated above, the closest approximation of the ratio of reverse saturation current in germanium diode to that in silicon diode is
- 1
- 5
- 4 $\times$103
- 8 $\times$103
A Silicon PN junction at a temperature of 20°C has a reverse saturation current of 10 pico-Amperes (pA). The reverse saturation current at 40°C for the same bias is approximately
- 30 pA
- 40 pA
- 50 pA
- 60 pA
n-type silicon is obtained by doping silicon with
- germanium
- aluminum
- boron
- phosphorus
The drain current of MOSFET in saturation is given by ID = K (VGS-VT) where K is constant.
The magnitude of the transconductance gm is
- $\dfrac{K(V_{GS}- V_T)^2}{V_{DS}}$
- 2K (VGS - VT)
- $\dfrac{I_d}{V_{GS} - V_{DS}}$
- $\dfrac{K (V_{GS} - V_T)^2 }{V_{GS}}$
For an n-channel enhancement type MOSFET, if the source is connected at a higher potential than that of the bulk, (i.e. VSB > 0) the threshold voltage VT of the MOSFET
- remains unchanged
- decreases
- changes polarity
- increases
The silicon sample with unit cross-sectional area shown below is in thermal equilibrium. The following information is given: T=300K, electronic charge=1.6x10-19C, thermal voltage=26mV and electron mobility = 1350cm2/V-s
The magnitude of the electric field at x = 0.5 $\mu$m is
- 1kV/cm
- 5kV/cm
- 10 kV/cm
- 26kV/cm
The source of a silicon (ni = 1010 per cm3) n – channel MOS transistor has an area of 1 sq $\mu m$ and a depth of 1 $\mu m$. If the dopant density in the source is 1019/cm3, the number of holes in the source region with the above volume is approximately.
- 107
- 100
- 10
- 0
The measured trans conductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at a constant drain voltage VD. Which of the following figures represents the expected dependence of gm on VG?
The silicon sample with unit cross-sectional area shown below is in thermal equilibrium. The following information is given: T=300K, electronic charge=1.6x10-19C, thermal voltage=26mV and electron mobility = 1350cm2/V-s
The magnitude of the electron drift current density at x = 0.5 $\mu$m is
- 2.16$\times$104 A/cm2
- 1.08$\times$104 A/cm2
- 4.32$\times$103 A/cm2
- .48$\times$102 A/cm2
A p +n junction has a built-in potential of 0.8 V. The depletion layer width at a reverse bias of 1.2V is 2 $\mu$m. For a reverse bias of 7.2 V, the depletion layer width will be
- 4 $\mu$m
- 4.9 $\mu$m
- 8 $\mu$m
- 12 $\mu$m
When the gate-to-source voltage (VGS) of a MOSFET with threshold voltage of 400 mV, working in saturation is 900 mV, the drain current in observed to be 1 mA. Neglecting the channel width modulation effect and assuming that the MOSFET is operating at saturation, the drain current for an applied VGS of 1400 mV is
- 0.5 mA
- 2.0 mA
- 3.5 mA
- 4.0 mA
The action of a JFET in its equivalent circuit can best be represented as a
- Current Controlled Current Source
- Current Controlled Voltage Source
- Voltage Controlled Voltage Source
- Voltage Controlled Current Source
Find the correct match between Group 1 and Group 2:
| Group 1 | Group 2 |
| E. Varactor diode | 1. Voltage reference |
| F. Pin diode | 2. High frequency switch |
| G. zener diode | 3. Tuned circuits |
| H. Schottky diode | 4. Current controlled attenuator |
- E - 4, F - 2, G - 1, H - 3
- E - 2, F - 4, G - 1, H - 3
- E - 3, F - 4, G - 1, H - 2
- E - 1, F - 3, G - 2, H – 4
The given figure is the voltage transfer characteristic of

- an NOMS inverter with enhancement mode transistor as load
- an NMOS inverter with depletion mode transistor as load
- a CMOS inverter
- a BJT inverter
Directions: Consider a silicon p - n junction at room temperature having the following parameters:
Doping on the n-side = 1 x 1017 cm-3
Depletion width on the n-side = 0.1 $\mu$m
The built-in potential of the junction
Depletion width on the p −side = 1.0 $\mu$m
Intrinsic carrier concentration = 1.4 x 1010 cm-3
Thermal voltage = 26 mV
Permittivity of free space = 8.85 x 10-14 F cm-1
Dielectric constant of silicon = 12
The built-in potential of the junction
- is 0.70 V
- is 0.76 V
- is 0.82 V
- Cannot be estimated from the data given
Directions : Consider a silicon p - n junction at room temperature having the following parameters:
Doping on the n-side = 1 x 1017 cm-3
Depletion width on the n-side = 0.1 $\mu$m
Depletion width on the p −side = 1.0 $\mu$m
Intrinsic carrier concentration = 1.4 x 1010 cm-3
Thermal voltage = 26 mV
Permittivity of free space = 8.85 x 10-14 F cm-1
Dielectric constant of silicon = 12
The peak electric field in the device is
- 0.15 MV. cm-1, directed from p −region to n −region
- 0.15 MV. cm-1, directed from n −region to p −region
- 1 80 MV. cm-1, directed from p-region to n −region
- 1.80 MV. cm-1, directed from n −region to p −region








