Online Test 2 - Digital Logic and Circuit Design

Essential prime implicants are prime implicants that cover an output of the function that no combination of other prime implicants is able to cover i.e., if we delete such elements then the property of group, quad, octet is destroyed. By drawing k map and by putting c on left side and a, b on right side we can find that a'c and ac' are essential prime implicants.

 [(XY’)’ NAND (YZ)’]= [(XY’)’ .(YZ)’]’ =XY’+YZ,  So None of X, Y, Z is redundant

 We can first convert to Binary, we get 110 101 111. Then convert binary to base 16, we get 1AF (0001 1010 1111).
(657)base 8=
Writing binary of each digit=> 110=6
=> 101=5
=> 111=7
Adding extra 0’s I beginning to make groups of 4 binary digits each
000110101111= 0001 1010 1111
In octal
0001 =1
1010 =A
1111 =F
So Ans is (1) part.

Address Bus of 8086 CPU is 20 bits.

Let the input carry to the first adder be denoted by C1.
Now, to calculate C2 we need = P1C1 + G1 = 4 gate levels (P1 takes 2 gate levels)
to calculate S1 we need = P1 XOR C1 = 2 + 2 = 4 gate levels.
Since it is a Carry look ahead adder, computing C3 , S2 doesn’t have to wait for carry output C2 from the previous adder as C2, C3 etc will get computed at the same time.
Now,
S2 is computed as = P2 XOR C2 = P2.C2′ + P2′.C2
= P2 (P1.C1 + G1 )’ + P2′ (P1.C1 + G1) [ notice that we are not using the output carry from first adder C2 anywhere here ]
which can be implemented using 4 gate levels.
also C3 can be computed by using 4 gate levels and so on…
so the overall propagation delay is 4 gate level as the outputs at Si , Ci are available at the respective full adders after 4 gate levels = 4 time units.

(123)5 = (x3)y
Converting both sides to decimal:
⇒ 25 + 10 + 3 = xy + 3
⇒ xy + 3 = 38
⇒ xy = 35
⇒ x = 5, y = 7
or , x = 7, y = 5 
∴ Total number of solutions: 2

The Flip Flop used here is a Positive edge triggered D Flip Flop, which means that only at the “rising edge of the clock” flip flop will capture the input provided at D and accordingly give the output at Q. And at other times of the clock the output doesn’t change. The output of D flip flop is same as input, i.e. Y=Q=D ( at the rising edge ).
Now, in the question above, 5 clock periods are given, and we have to find the output Q or Y in those clock periods.
First, let’s derive the boolean expression for the Logic gate.
which is :
D = AX + X’ Q’
Now,
In the 1st clock period, (i.e. when t = 0 to 1 )
here the clock has rising edge at t= 0, hence at this moment only, D flip flop will change its state.
In the 1st clock, X = 1, So, D = A. Now A logic line may have different levels at different clock periods, i.e. may be high or low, therefore we have to answer with respect to the ith clock period where Ai is the logic level ( high or low ) of logic line A in the ith clock.
So in the 1st clock period, A logic value should be A1 ( i.e. value of A in 1st clock period), but due to the delay provided by the Logic Gates ( Propagation Delay) the value of A used by Flip Flop is previous value of A only, i.e.it will capture the value of D resulted by using the logic line A in the 0th clock period, which is A0. Same happens with the value of X, i.e. instead of Xi, previous value of X is used in the in the ith clock period, which is Xi-1.
Now, In the 1st clock period value of X is same as in the 0th clock, i.e. logic 1. So, X = 1 ,and A = A0, therefore, D = A0, and hence Q = Y = A0
Similarly we have to do for other clock periods, i.e. instead of taking Ai and Xi, Ai-1 and Xi-1 need to be taken for getting the output in the ith clock period.
In the 2nd clock period, (i.e. when t = 1 to 2 )
X = 1 ( value in the previous clock), So, D = A1 ( value of A in the previous clock) , therefore Q = Y = A1
In the 3rd clock period, (i.e. when t = 2 to 3 )
X = 0 ( value in the previous clock,see the timing diagram), So, D = Q’ = A1′ , therefore Q = Y = A1′ ( because of the feedback line )
In the 4th clock period, (i.e. when t = 3 to 4 )
X = 1 ( value in the previous clock, ), So, D = A3 , therefore Q = Y = A3
In the 5th clock period, (i.e. when t = 4 to 5 )
X = 1 ( value in the previous clock ), so, D = A4 , therefore Q = Y = A4
Hence the output sequence is : A0 A1 A1′ A3 A4

512, 64, 8 and 0 are all powers of 8.
The proceeding number is translatable in second to an octal number.
$ 3 \times 8^3 + 7 \times 8^2 + 5 \times 8^1 + 3 \times 8^0 $
$ 3753_8 = 011 111 101 011_2 $

A shift-register converts parallel data to serial format (A-3). A multiplexer acts as a many-to-one switch, selecting one input from multiple (B-4). A decoder generates unique outputs for each input combination and can generate memory chip select signals (C-2).

For carry look ahead adder we know carry generate function—
Where

As we are having two 3 bits number to add so final carry out will be C3-
Putting value of Pi,Gi in 3

$C_3=(A_2.B_2)+(A_1.B_1)(A_2+B_2)+(A_0.B_0)(A_1+B_1)(A_2+B_2) (\text{TAKING }C0=0) $
$C_3=A_2.B_2 +A_1A_2B_1+A_1B_2B_1+(A_0B_0)(A_1A_2+A_1B_2+B_1A_2+B_1B_2) $
$C_3=A_2B_2+A_1A_2B_1+A_1B_2B_1+A_0A_1A_2B_0+A_0A_1B_0B_2+A_0A_2B_1B_0+A_0B_0B_1B_2 $