GATE Online Test 1 - Digital Circuits | Computer Science(CS)

A nibble is 4 bits. When adding two 4-bit numbers without an initial carry, the least significant bit (LSB) position only needs a half adder since there's no carry-in. The remaining 3 bit positions each require a full adder to handle the carry-out from the previous stage. Therefore, 3 full adders and 1 half adder are needed.

K = digit = ? ^{$\Rightarrow$} radix = r = 2; P = number = 52:39
$\Rightarrow$$K = [\log_r (P+1)] = \lceil \log_2(52139 + 1 ) \rceil = 16 $

$A \bar B+ AB \bar C + ABC(D + \bar D) \Rightarrow A \bar B+ ABC = A \bar B+ AB( C + \bar C)$
$\Rightarrow A \bar B+ AB = A(B + \bar B) = A$

In Gray code, the most significant bit (MSB) is always identical to the MSB of the corresponding binary number. This is a fundamental property of Gray code conversion - only the MSB remains unchanged, all other bits may change based on XOR operations with adjacent binary bits.

$101 \Rightarrow (1/2)(1) - 0 + (1/2)^3 \Rightarrow 0.5 +0 + 0.125 = 0.625$

$J_0K_0 = 00 \qquad Q_{0(n+1)} = Q_n = 1$
$J_1K_1 = 00 \qquad Q_{1(n+1)} = \bar Q_n = 1$
$J_2K_2 = Q_1 = 00 \qquad Q_{2(n+1)} = Q_n = 1$
$J_3K_3 = Q_2Q_1 = 00$
$Q_3Q_2Q_1Q_0 = 0011$

A 3-bit up counter using T flip-flops requires minimum gates when exploiting the toggle pattern. With unlimited fan-in, only 2 gates are needed: the first T flip-flop toggles every clock (no gate needed), while the second and third require enable logic that can be implemented with just 2 gates total using AND/OR combinations.

The minimum Sum of Products (SOP) form is X̄Ȳ + Z. Using Boolean algebra simplification or Karnaugh map: X̄ȲZ̄ + X̄ȲZ + X̄YZ + XȲZ + XYZ = X̄Ȳ(Z̄+Z) + X̄YZ + XȲZ + XYZ = X̄Ȳ + Z(X̄Y + XȲ + XY) = X̄Ȳ + Z(X̄Y + X(Ȳ+Y)) = X̄Ȳ + Z(X̄Y + X) = X̄Ȳ + Z(X + Y) = X̄Ȳ + XZ + YZ = X̄Ȳ + XZ + YZ. Further analysis shows X̄Ȳ + Z is the minimal form.

Adding two 16-bit numbers requires: 1 half adder for the LSB (no carry-in needed) and 15 full adders for the remaining bits (each must handle carry-in from the previous stage). This totals 16 adders for 16 bits. The half adder at position 0 generates the first carry-out, which becomes the carry-in for the full adder at position 1.

In this expression, AND and OR are bitwise operators. 42 in binary is 00101010, 72 is 01001000, 55 is 00110111. (42 OR 72) = 01101010 = 106. Then 106 AND 55 = 00100010 = 34. The result is 34.

$Y = \overline{ab}$
$= \overline { \overline {ab}} = ab$

To detect patterns 010 and 0001, we need states representing partial matches. State diagram needs: initial state (S0), after '0' (S1), after '01' (S2), after '010' (S3 - output 1), after '00' (S4), after '000' (S5), after '0001' (S6 - output 1). However, some states can be merged, and the minimal implementation requires 5 states to track all necessary prefix information without redundancy.

Given F(A,B) = Ā + B. We need F(f(x+y, y), z). First, f(x+y, y) substitutes for A, so Ā becomes f(x+y, y)̄. But we need to know what f is. If f is the OR function, then f(x+y, y) = (x+y) + y = x+y. Then F(f(x+y, y), z) = F(x+y, z) = (x+y)̄ + z = x̄·ȳ + z. However, the claimed answer is xȳ + z. This suggests f might be XOR or another operation. Based on the answer choice, the simplified expression is xȳ + z.