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Test 2 - Digital Logic | Computer Science(CS)

GATE Previous year Topic Wise Questions and Answers | Digital Logic

18 Questions Published
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Questions

Question 1 Multiple Choice (Single Answer)

The Boolean function x'y' + xy + x'y is equivalent to

  1. x' + y'
  2. x + y
  3. x + y'
  4. x' + y
Question 2 Multiple Choice (Single Answer)

If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and y are

  1. 8, 16
  2. 10, 12
  3. 9, 13
  4. 8, 11
Question 3 Multiple Choice (Single Answer)

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,...9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit $\ge$ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

  1. 2
  2. 3
  3. 4
  4. 5
Question 4 Multiple Choice (Single Answer)

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding?
(113.+−111.)+7.51
113.+(−111.+7.51)

  1. 9.51 and 10.0 respectively
  2. 10.0 and 9.51 respectively
  3. 9.51 and 9.51 respectively
  4. 10.0 and 10.0 respectively
Question 5 Multiple Choice (Single Answer)

Which are the essential prime implicates of the following Boolean function?
f (a,b,c) = a'c + ac' + b'c

  1. a'c and ac'
  2. a'c and b'c
  3. a'c only
  4. ac' and bc'
Question 6 Multiple Choice (Single Answer)

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncompensated forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
Assume that the carry network has been implemented using two-level AND-OR logic.

  1. 4 time units
  2. 6 time units
  3. 10 time units
  4. 12 time units
Question 7 Multiple Choice (Single Answer)

Let A = 11111010 and B 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

  1. 1100 0100
  2. 1001 1100
  3. 1010 0101
  4. 1101 0101
Question 8 Multiple Choice (Single Answer)

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

  1. Q = 0,Q' = 1
  2. Q = 1,Q' = 0
  3. Q = 1,Q' = 1
  4. Indeterminate states
Question 9 Multiple Choice (Single Answer)

Consider the following circuit.

Which one of the following is TRUE?

  1. f is independent of X
  2. f is independent of Y
  3. f is independent of Z
  4. None of X,Y,Z is redundant
Question 10 Multiple Choice (Single Answer)

The hexadecimal representation of 6578 is

  1. 1AF
  2. D78
  3. D71
  4. 32F
Question 11 Multiple Choice (Single Answer)

Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

  1. Q2'
  2. Q2+ Q1
  3. (Q1 $\oplus$ Q2)'
  4. Q1 $\oplus$ Q2
Question 12 Multiple Choice (Single Answer)

The switching expression corresponding to
f (A,B,C,D) = $\sum$(1,4,5,9,11,12) is

  1. BC'D' + A'C'D + AB'D
  2. ABC' + ACF + B'C'D
  3. ACD' + A'BC' + AC'D'
  4. A'BD + ACD' + BCD'
Question 13 Multiple Choice (Single Answer)

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE?

  1. It computes 1's complement of the input number
  2. It computes 2's complement of the input number
  3. It increments the input number
  4. It decrements the input number
Question 14 Multiple Choice (Single Answer)

Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0,Q1. Let the initial state be 00. The state transition sequence is

  1. $\underline{00 \rightarrow 11 \rightarrow 01 }$
  2. $\underline{00 \rightarrow 11 }$
  3. $\underline{00 \rightarrow 11 \rightarrow 01 \rightarrow 11 }$
  4. $\underline{00 \rightarrow 11 \rightarrow 01 \rightarrow 01 }$
Question 15 Multiple Choice (Single Answer)

Consider the following floating point format

Mantissa is a pure fraction is sign-magnitude form.

The decimal number 0.239 x 213 has the following hexadecimal representation without normalization and rounding off

  1. 0D 24
  2. 0D 4D
  3. 4D 0D
  4. 4D 3D
Question 16 Multiple Choice (Single Answer)

Consider the following floating point format

Mantissa is a pure fraction is sign-magnitude form.

The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0's are padded in while shifting a field. The normalized representation of the above number (0.239 x 213) is

  1. 0A 20
  2. 11 34
  3. 4D D0
  4. 4A E8
Question 17 Multiple Choice (Single Answer)

The range of integers that can be represented by an a bit 2's complement number system is

  1. −2n−1 to (2n−1− 1)
  2. −(2n−1− 1) to (2n−1− 1)
  3. −2n−1 to 2n−1
  4. −(2n−1+ 1) to (2n−1− 1)
Question 18 Multiple Choice (Single Answer)

Consider the following circuit involving a positive edge triggered D -FF.

Consider the following timing diagram. Let Ai represent the logic level on the line A in the i − th clock period.

Let A represent the complement of A. The correct output sequence on Y over the clock perids 1 through 5 is

  1. A0A1A1'A3A4
  2. A0A1A2'A3A4
  3. A1A2A2'A3A4
  4. A1A2'A3A4A5
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