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Test 2 - Computer Organization & Architecture | Computer Science(CS)

Description: GATE Previous year Topic Wise Questions and Answers | Computer Organization & Architecture
Number of Questions: 18
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Tags: Computer Organization and Architecture GATE CS
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For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to

  1. non-uniform distribution of requests

  2. arm starting and stopping inertia

  3. higher capacity of tracks on the periphery of the platter

  4. use of unfair arm scheduling policies


Correct Option: C
Explanation:

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches

  1. I only

  2. II only

  3. III only

  4. I, II and III


Correct Option: C
Explanation:

Multiple register windows with overlap causes a reduction in the number of memory accesses for instruction fetching .

Which of the following are NOT true in a pipelined processor?
I. Bypassing can handle all RAW hazards
II. Register renaming can eliminate all register carried WAR hazards
III. Control hazard penalties can be eliminated by dynamic branch prediction

  1. I and II only

  2. I and III only

  3. II and III only

  4. I, II and III


Correct Option: D
Explanation:

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

  1. I only

  2. II only

  3. I and II only

  4. I, II and III only


Correct Option: D
Explanation:

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?
I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache

  1. IV only

  2. I and IV only

  3. I, II and IV only

  4. I, II, III and IV


Correct Option: A
Explanation:

In an instruction execution pipeline, the earliest that the data TLB (Translation Look a side Buffer) can be accessed is

  1. Before effective address calculation has started

  2. During effective address calculation

  3. After effective address calculation has completed

  4. After data cache lookup has completed


Correct Option: B
Explanation:

TLB is used during effective address calculation in an instruction execution pipeline.

Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed

  1. I only

  2. II only

  3. III only

  4. II and III only


Correct Option: C
Explanation:

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The
cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this
machine begins as follows:
double ARR[1024] [1024];
int i, j;
/* Initialize array ARR to 0.0 */
for (i = 0; i < 1024; i++)
for (j = 0; j < 1024; j++)
ARR[i] [j] = 0.0;
The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page
0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR

The total size of the tags in the cache directory is

  1. 32 K bits

  2. 34 K bits

  3. 64 K bits

  4. 68 K bits


Correct Option: B
Explanation:

How many 32 K x 1 RAM chips are needed to provide a memory capacity of 256 Kbytes?

  1. 8

  2. 32

  3. 64

  4. 128


Correct Option: C
Explanation:

Delayed branching can help in the handling of control hazards

For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false

  1. The instruction following the conditional branch instruction in memory is executed

  2. The first instruction in the fall through path is executed

  3. The first instruction in the taken path is executed

  4. The branch takes longer to execute than any other instruction


Correct Option: B
Explanation:

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The
cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this
machine begins as follows:
double ARR[1024] [1024];
int i, j;
/* Initialize array ARR to 0.0 */
for (i = 0; i < 1024; i++)
for (j = 0; j < 1024; j++)
ARR[i] [j] = 0.0;
The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page
0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR

The cache hit ratio for this initialization loop is

  1. 0%

  2. 25%

  3. 50%

  4. 75%


Correct Option: C
Explanation:

A CPU generally handles an interrupt by executing an interrupt service routine

  1. As soon as an interrupt is raised

  2. By checking the interrupt register at the end of fetch cycle.

  3. By checking the interrupt register after finishing the execution of the current instruction.

  4. By checking the interrupt register at fixed time intervals.


Correct Option: C
Explanation:

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory
consists of 256 blocks and the request for memory blocks is in the following order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.
Which one of the following memory block will NOT be in cache if LRU replacement policy is used?

  1. 3

  2. 8

  3. 129

  4. 216


Correct Option: D
Explanation:

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The
cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this
machine begins as follows:
double ARR[1024] [1024];
int i, j;
/* Initialize array ARR to 0.0 */
for (i = 0; i < 1024; i++)
for (j = 0; j < 1024; j++)
ARR[i] [j] = 0.0;
The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page
0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR

Which of the following array elements has the same cache index as ARR [0] [0]?

  1. ARR [0] [4]

  2. ARR [4] [0]

  3. ARR [0] [5]

  4. ARR [5] [0]


Correct Option: B
Explanation:


A hard disk has 63 sectors per track, 10 platters each with 2 recording surfaces and 1000 cylinders. The address of a sector is given as a triple (c,h,s) , where c is the cylinder number, h is the surface number and s is the sector number. Thus, the 0th sector is addressed as (0,0,0), the 1st sector as (0,0,1), and so on

The address <400, 16, 29> corre4sponds tp sector number:

  1. 505035

  2. 505036

  3. 505037

  4. 505038


Correct Option: C
Explanation:

Delayed branching can help in the handling of control hazards

The following code is to run on a pipelined processor with one branch delay slot:
11 : ADD R2 $\leftarrow$ R7 + R8
12 : SUB R4 $\leftarrow$ R5 – R6
13 : ADD R1 $\leftarrow$ R2 + R3
14 : STORE Memory [R4] $\leftarrow$ R1
BRANCH to Label if R1 == 0
Which of the instructions 11, 12, 13 or 14 can legitimately occupy the delay slot without any other program modification?

  1. 11

  2. 12

  3. 13

  4. 14


Correct Option: B
Explanation:

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:

S1 S2 S3 S4
11 2 1 1 1
12 1 3 2 2
13 2 1 1 3
14 1 2 2 2

What is the number of cycles needed to execute the following loop?
For (I = 1 to 2) {I1; I2; I3; I4;}

  1. 16

  2. 23

  3. 28

  4. 30


Correct Option: D
Explanation:

A hard disk has 63 sectors per track, 10 platters each with 2 recording surfaces and 1000 cylinders. The address of a sector is given as a triple (c, h, s), where c is the cylinder number, h is the surface number and s is the sector number. Thus, the 0th sector is addressed as (0, 0, 0), the 1st sector as (0, 0, 1), and so on

The address of the 1039th sector is

  1. (0, 15, 31)

  2. (0, 16, 30)

  3. (0, 16, 31)

  4. (0, 17, 31)


Correct Option: C
Explanation:

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