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Computer Organization & Architecture - GATE Previous Year Questions
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Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
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A
O (n)
💡 Explanation:
The no. of gates used in n bit array multiplier (n x n) is 2n - 1. So. if every single gate takes unit delay, then total delay 0 (2n -1) = 0 (n) It is of linear order