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Digital Systems and Microprocessors

Digital Systems and Microprocessors

5 Questions Published
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Questions

Question 1 Multiple Choice (Single Answer)

In which memory design, the communication between CPU and cache is through a separate bus, and is isolated from the main system bus?

  1. Look through design
  2. Look aside design
  3. Write through
  4. Write back
  5. Write once
Question 2 Multiple Choice (Single Answer)

Which of the following contains the address of an instruction to be fetched?

  1. Program counter
  2. Instruction register
  3. Memory address register
  4. I/O address register
  5. I/O buffer register
Question 3 Multiple Choice (Single Answer)

Which of the following consists of the access time along with any additional time required, before a second access can commence?

  1. Cycle time
  2. Access time
  3. Transfer rate
  4. Sequencial
  5. Direct
Question 4 Multiple Choice (Single Answer)

In which mode, the effective address of the operand is the contents of a register or memory location whose address appears in the instruction?

  1. Direct Addressing Mode
  2. Immediate Addressing Mode
  3. Synchronous
  4. Asynchronous
  5. Indirect Addressing Mode
Question 5 Multiple Choice (Single Answer)

Which of the following divides the system into a number of modules and arrange them so that successive words in the address space are placed in different modules?

  1. Direct mapping
  2. Asociative mapping
  3. Set associative mapping
  4. Cache memory
  5. Memory interleaving
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