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Advanced Computer Architecture

Description: ACA
Number of Questions: 15
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Tags: ACA Computer Architect
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Which of the following terms is used in cache organisation when the addressed data or instruction is found in the cache during operation?

  1. Cache Miss

  2. Cache Hit

  3. Cache Struck

  4. Cache Read

  5. Cache Write


Correct Option: B
Explanation:

This term is used in cache organisation when the addressed data or instruction is found in the cache during operation.

Which of the following term refers to the translation of main memory address to the cache memory address?

  1. Physical address mode

  2. Virtual address mode

  3. Mapping

  4. Unified cache

  5. Hit ratio


Correct Option: C
Explanation:

Mapping refers to the translation of a main memory address to the cache memory address.

Which of the following level of parallelism is also called fine-grained parallelism?

  1. Parallelism at the loop level.

  2. Parallelism at the procedure level.

  3. Parallelism at the instruction level.

  4. Parallelism at the program level.

  5. Parallelism at the exit level.


Correct Option: C
Explanation:

This level of parallelism is also called fine-grained parallelism because available instructions are executed in parallel.

Which of the following strong consistency models is the one in which if the processes are executed in sequence, then the results are similar to the read write operations?

  1. Sequential consistency

  2. Strict consistency

  3. Casual consistency

  4. FIFO consistency

  5. Stack consistency


Correct Option: A
Explanation:

This consistency model is the one in which if the processes are executed in sequence, then the results are similar to the read write operations.

Which of the following addressing modes in 80X86 is the one in which an effective address is the contents of the base register?

  1. Absolute address

  2. Indexed Absolute Address

  3. Scaled Address

  4. Register Indirect Address

  5. Base Plus Index Plus Offset


Correct Option: D
Explanation:

In this addressing mode, the effective address is the contents of the base register.

Which of the following operations in pipeline instruction processing is performed first?

  1. Calculate operand address

  2. Fetch instruction

  3. Decode instruction

  4. Execute instruction

  5. Fetch operand


Correct Option: B
Explanation:

This is the first operation in pipeline instruction processing in which the next expected instruction is read into a buffer from cache memory.

Which of the following instruction sets in Instruction Set Architecture (ISA) consists of a variety of expert instructions and may just not be used in practical programs?

  1. RISC(Reduced Instruction Set Computer)

  2. CISC(Complex Instruction Set Computer)

  3. VLIM(Very Long Instruction Word)

  4. Multithreading

  5. Multitasking


Correct Option: B
Explanation:

This instruction set in Instruction Set Architecture (ISA) consists of a variety of expert instructions and may not just be used in practical programs.

Which of the following registers of the vector register processor are linked to the functional units with the help of a pair of crossbars?

  1. Vector register

  2. Scalar register

  3. Vector functional units

  4. Vector load and store unit

  5. Control unit


Correct Option: B
Explanation:

This register of the vector register processor is linked to the functional units with the help of a pair of crossbars.

Which of the following type of vector instruction is an operation that fetches the non-zero elements of a sparse vector from memory?

  1. Vector-Scalar instructions

  2. Vector-Vector instructions

  3. Gather and Scatter instructions

  4. Vector-Memory instructions

  5. Masking instructions


Correct Option: C
Explanation:

This type of vector instruction is an operation that fetches the non-zero elements of a sparse vector from memory.

Which of the following technique is the one by which the execution of multiple instructions can be overlapped?

  1. Hazards

  2. Freeze

  3. Pipelining

  4. Forwarding

  5. FIFO


Correct Option: C
Explanation:

Pipelining is the technique by which the execution of multiple instructions can be overlapped.

Which of the following hazards occur when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline?

  1. Structural hazards

  2. Control hazards

  3. Data hazards

  4. Cache miss

  5. Resource conflict


Correct Option: C
Explanation:

These hazards occur when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.

Which of the following parallelism refers to the way threads can communicate with other threads residing in other processors?

  1. Background processing

  2. Communication parallelism

  3. Computation parallelism

  4. Thread granularity

  5. Thread switch


Correct Option: B
Explanation:

This parallelism refers to the way threads can communicate with other threads residing in other processors.

Which of the following principles of multi-threading verifies the number of occurrences of thread switching?

  1. Communication latency

  2. The number of active threads

  3. Thread switch

  4. The numbers of remote reads in each thread

  5. Scalability


Correct Option: D
Explanation:

This principle of multi-threading verifies the number of occurrences of thread switching.

Which of the following interfaces in computer architecture gives a method for transferring information between internal memory and I/O devices?

  1. Bus interface

  2. Input-Output interface

  3. Response time

  4. Throughput

  5. RAID


Correct Option: B
Explanation:

This interface in computer architecture gives a method for transferring information between internal memory and I/O devices.

Which of the following terms in computer architecture is used in each computer having its own particular instruction code format?

  1. Decoding

  2. Fields

  3. Instruction set

  4. Cell

  5. Operation


Correct Option: C
Explanation:

Instruction set is the term used in instruction format.

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