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Computer Architecture

Description: Computer Architecture
Number of Questions: 15
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Tags: Logic Design System Computer Organization and Architecture Computer Architect
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If the output of a shift register is fed back to the input, then it is the result of which of the following?

  1. Johnson Counter

  2. Ring Counter

  3. Shift Register

  4. ADC

  5. DAC


Correct Option: B
Explanation:

If the output of a sift register is fed back to the input.

In which of the following modes is 'the datum is in the register' specified by the instruction in 8086 processor?

  1. Register Indirect Addressing Mode

  2. Register Relative Addressing Mode

  3. Relative Based Indexed Addressing Mode

  4. Intrasegment Direct Addressing Mode

  5. Register Addressing Mode


Correct Option: E
Explanation:

'The datum is in the register' is specified by the instruction in 8086 processor.

In which of the following addressing modes, the effective address is the sum of base register and an index register, both of which are specified by the instruction in 8086 processor?

  1. Relative Based Indexed Addressing Mode

  2. Register Relative Addressing Mode

  3. Based Indexed Addressing Mode

  4. Instruction

  5. Intersegment Direct Addressing Mode


Correct Option: C
Explanation:

The effective address is the sum of a base register and an index register, both of which are specified by the instruction in 8086 processor.

In which of the following modes, 16 bit effective address of the datum is a part of the instruction in 8086 processor?

  1. Register Indirect Addressing Mode

  2. Intersegment Direct Addressing Mode

  3. Direct Addressing Mode

  4. Operand

  5. Relative Based Index Addressing Mode


Correct Option: C
Explanation:

The 16 bit effective address of the datum is part of the instruction in 8086 processor.

In which of the following addressing modes, the datum is either 8 or 16 bits long and is part of the instruction in 8086 processor?

  1. Relative Based Indexed Addressing Mode

  2. Intrasegment Direct Addressing Mode

  3. Register Relative Addressing Mode

  4. Immediate Addressing Mode

  5. Instruction


Correct Option: D
Explanation:

The datum is either 8 bits or 16 bits long and is part of the instruction in 8086 processor.

Which of the following delays data by one clock time for each stage?

  1. Serial In, Serial Out Shift Register

  2. Serial In, Parallel Out Shift Register

  3. Shift Register

  4. Resolution

  5. Conversion Rate


Correct Option: A
Explanation:

It delays data by one clock time for each stage.

In which of the following logic gates, the output is false only when both the inputs are true?

  1. AND Logic

  2. NAND Logic

  3. OR Logic

  4. NOT Logic

  5. Resolution


Correct Option: B
Explanation:

Here, the output is false only when both the inputs are true.

In which of the following, the contents of IP are replaced by the effective branch address and it may be used only in unconditional branch instructions in 8086 processor?

  1. Intrasegment Indirect Addressing Mode

  2. Intersegment Indirect Addressing Mode

  3. Register Relative Addressing Mode

  4. Relative Based Indexed Addressing Mode

  5. Stack Pointer


Correct Option: A
Explanation:

Here, the contents of IP are replaced by the effective branch address and it may be used only in unconditional branch instructions in 8086 processor.

In which of the following classifications of shift register, the mode control may be multiple inputs, controls parallel loading vs shifting?

  1. Serial In, Parallel Out Shift Register

  2. Shift Register

  3. Johnson Counter

  4. Parallel In, Parallel Out Shift Register

  5. Step Recovery


Correct Option: D
Explanation:

The mode control, which may be multiple inputs, controls parallel loading vs shifting.

In which of the following logics, the output is true only when any one of the inputs were true, and output is false if both inputs are the same logic?

  1. OR Logic

  2. NOT Logic

  3. Ex-OR Logic

  4. AND Logic

  5. Step Recovery


Correct Option: C
Explanation:

The output is true only when any one of the inputs were true and output is false if both inputs are at the same logic.

In which of the following, the branch contains the address to be used, if the branch occurs, as two byte following the instruction byte in 8085 processor?

  1. Register Indirect Branch Addressing Mode

  2. Direct Branch Addressing Mode

  3. Direct Addressing Mode

  4. Intersegment Direct

  5. Register Selector


Correct Option: B
Explanation:

The branch contains the address to be used, if the branch occurs, as two bytes following the instruction byte in 8085 processor.

In which of the following, the output is true only when both the inputs are false?

  1. NOR Logic

  2. OR Logic

  3. NOT Logic

  4. AND Logic

  5. Resolution


Correct Option: A
Explanation:

The output is true only when both the inputs are false.

Which of the following can specify the address of the next instruction to be executed, if it is not the one immediately following the branch, in two ways in 8085 processor?

  1. Register Indirect Branch Addressing Mode

  2. Branch Instruction Type Addressing Mode

  3. Direct Addressing Mode

  4. Instruction

  5. Intersegment Indirect Addressing Mode


Correct Option: B
Explanation:

These instructions can specify the address of the next instruction to be executed, if it is not the one immediately following the branch , in two ways in 8085 processor.

In which of the following logic gates is the output true only when both the inputs were either true or false?

  1. NOT Logic

  2. AND Logic

  3. Ex-NOR Logic

  4. OR Logic

  5. ADC


Correct Option: C
Explanation:

The outputs is true only when both the inputs were either true or false.

Which of the following modes results in three byte instruction, and first byte contains the instruction itself and second and third byte contain the data, either as a single 8 bit value or 16 bit value in 8085 processor?

  1. Direct Addressing Mode

  2. Register Indirect Branch Addressing Mode

  3. Register Relative Addressing Mode

  4. Relative Based Indexed Addressing Mode

  5. Immediate Mode


Correct Option: E
Explanation:

It results in two or three bytes instruction in which first byte contains the instruction itself and the second and third bytes contain the data, either as a single 8 bit value or a 16 bit value in 8085 processor.

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