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Computer Organization Architecture

Description: Logical system design Quiz
Number of Questions: 15
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Tags: Logical system design Computer Organization and Architecture Computer Architect
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In which of the following modes, the effective branch address is the contents of a register or memory location that is accessed by any data related addressing modes except the immediate mode in 8086 processor?

  1. Immediate Addressing Mode

  2. Direct Addressing Mode

  3. Intrasegment Indirect Addressing Mode

  4. Register Indirect Mode

  5. Instruction


Correct Option: C
Explanation:

The effective branch address is the contents of a register or memory location that is accessed using any data related addressing modes except the immediate mode.

Which of the following is a measure of how quickly an ADC changes its output to match a large, sudden change in the analog input?

  1. Resolution

  2. Step Recovery

  3. Aliasing

  4. ADC

  5. DAC


Correct Option: B
Explanation:

It is a measure of how quickly an ADC changes its output to match a large, sudden change in the analog input.

Which of the following is used to provide a means of branching from one code segment to another in 8086 processor?

  1. Intersegment Direct Addressing Mode

  2. Immediate Addressing Mode

  3. Direct Addressing Mode

  4. Stack Pointer

  5. Instruction


Correct Option: A
Explanation:

It's purpose is to provide a means of branching from one code segment to another in 8086 processor.

In which addressing mode, the branch specifies a register pair, which will contain the address for the branch in 8085 processor?

  1. Register Addressing Mode

  2. Direct Branch Addressing Mode

  3. Register Indirect Branch Addressing Mode

  4. DAC

  5. Flash Type ADC


Correct Option: C
Explanation:

The branch specifies a register pair which will contain the address for the branch in 8085 processor.

Which of the following uses fewer unique resistor values in DAC design, where there was a requirement of several different precise input resistor values?

  1. Binary Weighted Input DAC

  2. R-2R Ladder DAC

  3. ADC

  4. Resolution

  5. Nyquist Frequency


Correct Option: B
Explanation:

It uses fewer unique resistor values in former DAC design, where there was the requirement of several different precise input resistor values.

Which of the following replaces the contents of IP and CS with the contents of two consecutive words in memory that are referenced using any data related addressing modes, except the immediate and register modes in 8086 processor?

  1. Immediate Addressing Mode

  2. Register Addressing Mode

  3. Direct Mode

  4. Operand

  5. Intersegment Indirect Addressing Mode


Correct Option: E
Explanation:

It replaces the contents of IP and CS with the contents of two consecutive words in memory that are referenced using any data related modes except the immediate and register modes in 8086 processor.

Which circuit makes use of a free running counter and connect the output of a free running binary counter to the input of a DAC, then compare the analog output of the DAC with the analog input signal to be digitized?

  1. Flash Type ADC

  2. Digital Ramp ADC

  3. Binary Weighted Input DAC

  4. Resolution

  5. Nyquist Frequency


Correct Option: B
Explanation:

This circuit makes use of a free running counter and connect the output of a free running binary counter to the input of a DAC, then compare the analog output of the DAC with the analog input signal go be digitized.

In which of the following, the effective address is the sum of an 8 bit or 16 bit displacement and a based indexed address in 8086 processor?

  1. Immediate Addressing Mode

  2. Based Indexed Addressing Mode

  3. Relative Based Indexed Addressing Mode

  4. Instruction

  5. Stack Pointer


Correct Option: C
Explanation:

The effective address is the sum of an 8 bit or 16 bit displacement and a based indexed address in 8086 processor.

In which of the following, the effective address is the sum of an 8 or 16 bit displacement and the contents of a base register or an index register in 8086 processor?

  1. Register Addressing Mode

  2. Register Relative Addressing Mode

  3. Based Index Addressing Mode

  4. Immediate Addressing Mode

  5. Operand


Correct Option: B
Explanation:

The effective address is the sum of an 8 or 16 bit displacement and the contents of a base register or an index register in 8086 processor.

In which of the following, a very special counter circuit is used, which count by trying all values of bits starting with the most significant bits and finishing at the least significant bits?

  1. Successive Approximation ADC

  2. Flash Type ADC

  3. Binary Weighted Input DAC

  4. Aliasing

  5. Nyquist Frequency


Correct Option: A
Explanation:

In the circuit, a very special counter circuit is used, which counts by trying all values of bits starting with the most significant bits and finishing at the least significant bits.

Which of the following may be used with either conditional or unconditional branching, but a conditional branch instruction hasonly an 8 bit displacement in 8086 processor?

  1. Register Addressing Mode

  2. Immediate Addressing Mode

  3. Intrasegment Direct Addressing Mode

  4. Control Unit

  5. Register Indirect Mode


Correct Option: C
Explanation:

It may be used with either conditional or unconditional branching, but a conditional branch instruction can have only an 8 bit displacement in 8086 processor.

In which ADC, an integrator circuit is driven positive and negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts at the end of every cycle?

  1. Flash Type ADC

  2. R-2R Ladder DAC

  3. Binary Weighted Input DAC

  4. Dual Slope Integrator ADC

  5. Resolution


Correct Option: D
Explanation:

In the Dual Slope Converter, an integrator circuit is driven positive and negative in alternative cycles to ramp down and up, rather than being reset to 0 volts at the end of every cycle.

In which addressing mode, the effective address of the datum is in the base register or an index register that is specified by the instruction in 8086 processor?

  1. Register Addressing Mode

  2. Direct Addressing Mode

  3. Register Indirect Addressing Mode

  4. Instruction Register

  5. Register Selector


Correct Option: C
Explanation:

The effective address of the datum is in the base register or an index register that is specified by the instruction in 8086 processor.

Which mode creates three byte long instructions and the first byte contains the operation to be performed and the second and third bytes contain the address in memory in 8085 processor?

  1. Register Mode

  2. Register Indirect Mode

  3. Register Indirect Branch Mode

  4. Direct Mode

  5. Operand


Correct Option: D
Explanation:

This mode creates three byte long instructions and first byte contains the operation to be performed and second and third bytes contain the address in memory in 8085 processor.

In which ADC, an op-amp based circuit, called an integrator to generate a sawtooth waveform is used, instead of the use of a DAC with a ramped output?

  1. Binary Weighted Input DAC

  2. Flash Type ADC

  3. Resolution

  4. Single Slope Integrating ADC

  5. DAC


Correct Option: D
Explanation:

In Single Slope Integrating ADC an op-amp based circuit, called an integrator to generate a sawtooth waveform is used, instead of the use of a DAC with a ramped output.

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