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Digital Logics (GATE)

Covers boolean algebra, combinational and sequential circuits, flip-flops, counters, and digital circuit design principles

12 Questions Published
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Questions

Question 1 Multiple Choice (Single Answer)

JK master-slave flip-flop resolves the race problem using two flip-flops. These flip-flops are connected in which of the following patterns?

  1. Cascaded to each other and clock is applied to master flip-flop
  2. Cascaded to each other, but the clock is applied to both master and slave simultaneously
  3. Cascaded to each other and the outputs of master flip-flop are cross-coupled to inputs of slave
  4. Crossed-coupled to each other
  5. None of these
Question 2 Multiple Choice (Single Answer)

Using De Morgan's theorem, find the solution of the expression ((A + B)' + C')'.

  1. (A + B + C)(A . B . C)
  2. (A + B) . C
  3. (A + B)' . C
  4. ((A + B) . C)'
  5. (A + B) + C
Question 3 Multiple Choice (Single Answer)

Which of the following devices selects one line as output out of three input lines using its select logic?

  1. Encoder
  2. Decoder
  3. Selector
  4. Multiplexer
  5. Demultiplexer
Question 4 Multiple Choice (Single Answer)

A two-input XOR gate can also be used as

  1. OR gate
  2. Full adder logic chip
  3. Half adder logic chip
  4. NOR-AND gate
  5. NAND gate
Question 5 Multiple Choice (Single Answer)

Which of the following is a universal gate?

  1. AND
  2. OR
  3. XOR
  4. NOT
  5. NAND
Question 6 Multiple Choice (Single Answer)

One can convert an SR flip-flop into a D flip-flop when

  1. SR terminals are shorted to each other
  2. both inputs of the SR are kept open and a clock is applied
  3. a NOT gate is connected between the SR inputs
  4. S is made 0 and R is made 0
  5. D flip-flop cannot be made by SR flip-flop.
Question 7 Multiple Choice (Single Answer)

In asynchronous counter, the total propagation delay is n * tpd, while in synchronous counter, it is tpd. Why?

  1. The propagation delay occurs due to late arrival of the clock in the flip-flop and its own delay.
  2. Total propagation delay is tpd only.
  3. No propagation delay since the clock is available at the same time to all the flip-flops.
  4. Propagation delay is tpd + (n - 1).
  5. Propagation delay does not depend on the clock.
Question 8 Multiple Choice (Single Answer)

If a level clock is applied to a negative edge-triggered D flip-flop having 1 at D input, then what is the output q?

  1. 1
  2. 0
  3. A race condition arises.
  4. The output will not change.
  5. The output will change.
Question 9 Multiple Choice (Single Answer)

Tri-state buffers are required to connect two or more I/O devices on the bus. Why do we need tri-state buffers?

  1. Tri-state buffers are not required.
  2. Tri-state buffers provide a highly resistive output when their corresponding I/O devices are not selected.
  3. Tri-state buffers are required to provide high power to the bus.
  4. Tri-state buffers create longer delays.
  5. Tri-state buffers reduce the size of the gate.
Question 10 Multiple Choice (Single Answer)

Which of the following is not a part of combinational circuit?

  1. Output capacity
  2. Input capacity
  3. Storage capacity
  4. Capacity to drive more than one output
  5. Capacity to have controlled outputs
Question 11 Multiple Choice (Single Answer)

Tri-state BJT works as a buffer. What are the outputs of this buffer?

  1. Level 1, level 0, short
  2. Level 1, level 0, high resistance
  3. Level 1, level 0, level 1
  4. Level 1, level 0, level 0
  5. Level 0, high resistance, high resistance
Question 12 Multiple Choice (Single Answer)

While designing a counter, the state of the counter is represented by which of the following?

  1. Truth table
  2. K-map
  3. State diagram
  4. Excitation table
  5. Code table
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