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Computer Architecture

Description: This test consists of questions related to Computer Architecture concept, practice questions for Information Technology, GATE exam preparation
Number of Questions: 18
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In Direct Memory Access, _______ is responsible to manage the data transfer.

  1. data controller

  2. DMA controller

  3. device driver

  4. processor

  5. none of the above


Correct Option: B
Explanation:

DMA controller is like a special hardware in Direct Memory Access to manage the data transfer.

Which of the following is/are the use(s) of registers in DMA controller?

  1. Word count

  2. Store the starting address

  3. Status of the operation

  4. All of the above

  5. Only (1) and (2)


Correct Option: D
Explanation:

Yes, all of the above are the uses of the registers in DMA controller.

Which of the following transfer modes does not need the CPU intervention during data transfer?

  1. Interrupt initiated Input - Output

  2. Direct memory access

  3. Programmed Input - Output

  4. Both (2) and (3)

  5. None of the above


Correct Option: B
Explanation:

In this transfer mode, the interface transfers data into and out of the memory unit through the memory bus and it does not need the CPU's intervention during this transfer.

How many registers does a DMA controller has?

  1. 4

  2. 3

  3. 2

  4. 1

  5. None of the above


Correct Option: B
Explanation:

DMA controller uses the registers to store the starting address, word count and the status of the operation.
Option (2) is true.

Which of the following lines in a control bus is used to synchronize the data between the CPU and a device?

  1. Transfer ACK

  2. Bus request

  3. Bus grant

  4. Interrupt request

  5. Clock signals


Correct Option: E
Explanation:

The signal on this line indicates the synchronization of data between the CPU and the device.

Which of the following buses is used to carry commands from the CPU?

  1. Address bus

  2. Control bus

  3. Data bus

  4. Memory bus

  5. Both (1) and (2)


Correct Option: B
Explanation:

Yes, the control bus carries the commands from the CPU.

Which of the following buses is responsible to transfer the data to and from the memory or from the CPU to other components of the computer system?

  1. Address bus

  2. Control bus

  3. Data bus

  4. Both (2) and (3)

  5. None of the above


Correct Option: C
Explanation:

The Data bus transfers the data to and from the memory or from the CPU to other components of the computer system.

Which of the following buses is used to find the information about the devices, which are going to communicate with the CPU?

  1. Address bus

  2. Control bus

  3. Data bus

  4. Memory bus

  5. None of the above


Correct Option: A
Explanation:

The Address bus carries the information about the devices which are going to communicate with CPU.

Which of the following is the role of Memory Data Register (MDR)?

  1. It is used to store the memory address from which data will be fetched to the CPU.

  2. It is used to store the memory address to which the data will sent and stored.

  3. It is used to hold the memory data for the data bus.

  4. It is used to store the data in main memory.

  5. None of the above


Correct Option: C
Explanation:

This is true about Memory Data Register.

Which of the following registers holds the current instruction being executed?

  1. Program Counter

  2. Memory Address Register

  3. Memory Data Register

  4. Interrupt Register

  5. None of the above


Correct Option: E
Explanation:

None of the above options are true according to the question. The Current Instruction Register (CIR) is used to hold the current instruction being executed.

Which of the following is a false statement?

  1. The stack pointer (SP) is used to hold the address of top of element of the stack.

  2. A stack can be implemented in a random access memory (RAM) attached to a CPU.

  3. A stack is incremented after fetching an instruction.

  4. A stack can be arranged in a collection of registers.

  5. None of the above


Correct Option: C
Explanation:

This is a false statement as the Program Counter register is incremented on fetching of the instruction.

Which of the following registers contains the result of arithmetic and logical operations?

  1. Program Counter (PC)

  2. Current Instruction Register (CIR)

  3. Status Register

  4. Accumulator

  5. Interrupt Register


Correct Option: D
Explanation:

This register contains the result of arithmetic and logical operation.

Which of the following uses RISC (Reduced Instructions Set Computer)?

  1. Smartphone

  2. Tablet

  3. Computer

  4. All of the above

  5. Both (1) and (2)


Correct Option: D
Explanation:

Yes, all of the above use RISC.

Which of the following statement(s) is/are not true?

  1. CISC (Complex Instruction Set Computer) emphasis on hardware.

  2. RISC (Reduced Instruction Set Computer) emphasis on software.

  3. RISC software based instruction set has more then one clock to execute the micro program.

  4. CISC includes multi-clock complex instructions.

  5. None of the above


Correct Option: E
Explanation:

All of the above are true.

How many bits for an instruction set does an Advanced RISC Machine (ARM) have?

  1. 16 bits

  2. 32 bits

  3. 64 bits

  4. 128 bits

  5. 12 bits


Correct Option: B
Explanation:

ARM is a 32-bit reduced instruction set computer.

Which of the following is an example of RISC (Reduced Instruction Set Computer) processor?

  1. Pentium

  2. Pentium II

  3. MIPS

  4. Intel 386

  5. All of the above


Correct Option: E
Explanation:

Yes, all of the above are true.

Which of the following is/are true statement(s)?

  1. Serial data transfer communication has slower speed as compared to parallel data transfer communication.

  2. Parallel data transfer communication has short distance.

  3. Serial data transfer communication has longer distance.

  4. All of the above

  5. Both (1) and (2)


Correct Option: D
Explanation:

All of the above options are true statements.

Which of the following is not a characteristic of RISC (Reduced Instruction Set computer) processor?

  1. It has relatively few instructions.

  2. It has relatively few addressing modes.

  3. It has fixed length instructions.

  4. It has a single cycle instruction execution.

  5. None of the above


Correct Option: E
Explanation:

All of the above are the characteristics of RISC (Reduced Instruction Set computer) processor.

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