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Computer Organization and Architecture (NCO)

Description: CO
Number of Questions: 15
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Tags: COA Computer Architect
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___________ bus permanently assigns to either one function or to a physical subset of components.

  1. Dedicated

  2. Clock

  3. Interrupt request

  4. Request

  5. I/O write


Correct Option: A
Explanation:

This type of bus permanently assigns to either one function or to a physical subset of components.

 
 

The state in instruction cycle that determines the address of the next instruction to be executed is

  1. operand address calculation

  2. instruction address calculation

  3. instruction fetch

  4. operand fetch

  5. operand store


Correct Option: B
Explanation:

This state in instruction cycle determines the address of the next instruction to be executed.

 

The _______________ component of 8085 microprocessor is a collection of registers that are user-visible and help to store the operands or result of the operation.

  1. instruction register

  2. program counter

  3. register array

  4. stack pointer

  5. address/data buffer


Correct Option: C
Explanation:

This component of 8085 microprocessor is a collection of registers that are user-visible and help to store the operands or result of the operation.

 
 

The _________ design issue in designing an instruction set takes care of instruction length, number of addresses, size of various fields and so on.

  1. operation repertoire

  2. data types

  3. instruction format

  4. register

  5. addressing


Correct Option: C
Explanation:

This design issue in designing an instruction set takes care of instruction length, number of addresses, size of various fields and so on.

 
 

The __________ register of the CPU contains a word of data to be written to memory or the word most recently used.

  1. MAR

  2. PC

  3. IR

  4. MBR

  5. I/O AR


Correct Option: D
Explanation:

This register of the CPU contains a word of data to be written to memory or the word most recently used.

 
 

The _____________ is a method in which a computer makes it possible to call and return values from subroutines.

  1. stack

  2. queue

  3. subroutine linkage

  4. immediate addressing mode

  5. lists


Correct Option: C
Explanation:

This is a method in which a computer makes it possible to call and return values from subroutines.

 
 

The ____________ task performed by the CPU is the one in which the results of an execution may require writing data to memory or an I/O module.

  1. fetch data

  2. process data

  3. write data

  4. fetch instruction

  5. interpret instruction


Correct Option: C
Explanation:

This task performed by the CPU is the one in which the results of an execution may require writing data to memory or an I/O module.

 
 

_______________ memory cell uses a single transistor and a capacitor to store a bit of data.

  1. SRAM

  2. DRAM

  3. ROM

  4. PROM

  5. EPROM


Correct Option: B
Explanation:

This type memory cell uses a single transistor and a capacitor to store a bit of data.

 
 

The _____________ in accessing RAM consists of the access time plus any additional time required before a second access can commence.

  1. cycle time

  2. transfer time

  3. access time

  4. waiting time

  5. throughput rate


Correct Option: A
Explanation:

This time in accessing RAM consists of the access time plus any additional time required before a second access can commence.

 
 

_____________ in computer architecture implements a stack with registers and the operands of the ALU are always the top two registers of the stack, and the result from the ALU is stored in the top register of the stack.

  1. The accumulator machine

  2. The stack machine

  3. The load/store machine

  4. Flags

  5. Pop


Correct Option: B
Explanation:

This machine in computer architecture implements a stack with registers and the operands of the ALU are always the top two registers of the stack, and the result from the ALU is stored in the top register of the stack.

 
 

The ___________ in the allocation of addressing bits determines that each operand may require its own mode indicator or the use of indicator is limited to one of the address fields.

  1. number of addressing modes

  2. number of operands

  3. number of register set

  4. address range

  5. address granularity


Correct Option: B
Explanation:

This factor in the allocation of addressing bits determine that each operand may require its own mode indicator or the use of indicator is limited to one of the address fields.

 
 

The _____________ type of memory access is the one in which each addressable location in memory has a unique physically wired in addressing mechanism.

  1. sequential

  2. direct

  3. random

  4. associative

  5. indirect


Correct Option: C
Explanation:

This type of memory access is the one in which each addressable location in memory has a unique physically wired addressing mechanism.

 
 

The ____________ flag bits supported by the 8085 CPU are set when the result of ALU operation is zero.

  1. S

  2. P

  3. CY

  4. Z

  5. AC


Correct Option: D
Explanation:

This flag bit supported by the 8085 CPU is set when the result of ALU operation is zero.

 
 

The ______________ DMA transfer mode is the one in which DMA transfers at the fastest possible rate as long as the I/O device asserts its DMA request.

  1. block

  2. demand

  3. single

  4. bus

  5. flyby


Correct Option: B
Explanation:

This DMA transfer mode is the one in which DMA transfers at the fastest possible rate as long as the I/O device asserts its DMA request.

 
 

The ____________ addressing mode is the one in which the operand is in memory location and the address of this location is given explicitly in the instruction.

  1. immediate

  2. direct

  3. indirect

  4. register

  5. stack


Correct Option: B
Explanation:

This addressing mode is the one in which the operand is in memory location and the address of this location is given explicitly in the instruction.

 
 

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