aliensbrain
  • Home
  • Study
  • Quizzes
  • 🎤AI Practicefree
  • Notebooks
  • Community
  • Sign in
Multiple choice

In a positive edge triggered JK flip-flop, a low J and low K produces

  1. no change

  2. low state

  3. high state

  4. toggle

Reveal answer Fill a bubble to check yourself
A Correct answer
Explanation

In a JK flip-flop, when both J and K are low (0), the flip-flop holds its previous state - no change occurs at the output. This is the memory/hold state.

Keep practicing — related questions

  • The present output Qn of an edge triggered JK flip-flop is logic 0. If J = 1, then Qn + 1
  • For each of the positive edge-triggered J - K flip flop used in the following figure, the propagation delay...
  • Consider the following circuit. ![Flip Flop][1] The flip-flops are positive edge triggered D FFs. Each stat...
  • A JK flip-flop has its J input connected to logic level 1 and its input to the Q output, a clock pulse is f...
  • If a level clock is applied to a negative edge-triggered D flip-flop having 1 at D input, then what is the ...
  • Consider the following circuit ![](https://i.imgur.com/pkTxulP.png) The flip-flops are positive edge trigge...
  • What will be the output of the following code snippet? main() { int num=1; clrscr(); for(j=1;j<=6;j++) { fo...
  • Who among the following were the members of the Drafting Committee of the Constitution? (1) K. M. Munshi (2...
Advertisement
© Aliensbrain | all rights reserved
  • About
  • Contact
  • Terms and Condition
  • Privacy Policy